Developer Guide and Reference


Engine Initialization and Finalization

Unlike the simple
function, vector random number generators in the Short Vector Random Number Generator (SVRNG) library require the initialization of an engine before the first generator run. This is due to the fact that a number of initialization values called the "vector state" of the engine must be pre-computed to perform effective vector generation. Once computed that vector state is retained and updated in memory as more numbers are generated. When no more random numbers are needed, that memory can be deallocated. The next few topics provide the functions used to allocate memory, initialize, and deallocate memory for all supported SVRNG engines.
The SVRNG library supports the following engines from the C++11 standard and the Intel® Math Kernel Library (Intel® MKL) vector statistics random number generator collection:
  • rand0
    (C++11 standard)
  • rand
    (C++11 standard)
  • mcg31m1
    (Intel® MKL)
  • mcg59
    (Intel® MKL)
  • mt19937
    (Intel® MKL and C++11 standard)
For more information on the "figures of merit" for these random number generator engines read the "Basic Random Generator Properties and Testing Results" section of the
Notes for Intel® MKL Vector Statistics
document (see the introduction).
For each engine there is a simple and extended version of the initialization function. Simple initialization has one parameter, the "seed", and constructs the rest of the vector state to generate the proper sequence for the engine type. The extended versions of the initialization functions, with the "_ex" suffix, use multiple constants to set generator state values. The application notes in the description of each engine provide more detail on how these constants are used. The usual case for extended initialization requires enough constants to fill a SIMD register with 64-bit values on the system which the program is intended to run. The following table sums up the width (SIMD_WIDTH) of the SIMD registers used by the instructions sets for which the SVRNG intrinsics are optimized:
Instruction set
Intel® Streaming SIMD Extensions 2 (Intel® SSE2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
Intel® Initial Many Integrated Core Instructions (Intel® IMIC Instructions)