Developer Guide and Reference

Contents

Using Intel's valarray Implementation

Intel's valarray implementation allows you to declare huge arrays for parallel processing. Improved implementation of valarray is tied up with calling the IPP libraries that are part of Intel® Integrated Performance Primitives (Intel® IPP).

Using valarray in Source Code

To use valarrays in your source code, include the valarray header file,
<valarray>
. The
<valarray>
header file is located in the path
<installdir>/perf_header
.
The example code below shows a valarray addition operation (+) specialized through use of Intel's implementation of valarray:
#include <valarray> void test( ) { std::valarray<float> vi(N), va(N); … vi = vi + va; //array addition … }
To use the static merged library containing all CPU-specific optimized versions of the library code, you need to call the
ippStaticInit
function first, before any IPP calls. This ensures automatic dispatch to the appropriate version of the library code for Intel® processor and the generic version of the library code for non-Intel processors at runtime. If you do not call
ippStaticInit
first, the merged library will use the generic instance of the code. If you are using the dynamic version of the libraries, you do not need to call
ippStaticInit
.

Compiling valarray Source Code

To compile your valarray source code, the compiler option,
/Quse-intel-optimized-headers
(for Windows*) or
-use-intel-optimized-headers
(for Linux*
and
macOS*
), is used to include the required valarray header file and all the necessary IPP library files.
The following examples illustrate how to compile and link a program to include the Intel valarray replacement header file and link with the Intel® IPP libraries. Refer to the Intel® IPP documentation for details.
In the following examples, "merged" libraries refers to using a static library that contains all the CPU-specific variants of the library code.

Windows* OS examples:

The following command line performs a one-step compilation for a system based on IA-32 architecture, running Windows OS:
icl /Quse-intel-optimized-headers source.cpp
The following command lines perform separate compile and link steps for a system based on IA-32 architecture, running Windows OS:
DLL (dynamic):
icl /Quse-intel-optimized-headers /c source.cpp
icl source.obj /Quse-intel-optimized-headers
Merged (static):
icl /Quse-intel-optimized-headers /Qipp-link:static /c source.cpp icl source.obj /Quse-intel-optimized-headers /Qipp-link:static

Linux* OS examples:

The following command line performs a one-step compilation for a system based on Intel® 64 architecture, running Linux OS:
icpc -use-intel-optimized-headers source.cpp
The following command lines perform separate compile and link steps for a system based on Intel® 64 architecture, running Linux OS:
so (dynamic):
icpc -use-intel-optimized-headers -c source.cpp
icpc source.o -use-intel-optimized-headers -shared-intel
Merged (static):
icpc -use-intel-optimized-headers -c source.cpp
icpc source.o -use-intel-optimized-headers
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804