• 19.1
  • 12/16/2019
  • Public Content
Contents

Convenience and Correctness

Users can include a single header file
sdlt.h
that includes all the supported public features, or users can include the individual headers of features they will be using (which might build faster). In other words,
#include <sdlt/sdlt.h>
instead of
#include <sdlt/primitive.h> #include <sdlt/soa1d_container.h>
For convenience, SDLT provides a macro to encapsulate
#pragma forceinline recursive
.
SDLT_INLINE_BLOCK
SDLT reduces overhead by trusting the programmer to pass it valid values for template and function parameters. Adding conditional checks inside of a SIMD loop can cause unnecessary code generation and inhibit vectorization by creating multiple exit points in a loop. To assist in verifying that a program is indeed passing valid values to SDLT, the programmer can add a compilation flag to their build to define
SDLT_DEBUG=1
.
-DSDLT_DEBUG=1
If
_DEBUG
is defined and
SDLT_DEBUG
has not been defined to 0 or 1, then
SDLT_DEBUG
is automatically set to 1. When set to 1, every operator[] is bounds checked and all addresses are validated for correct alignment. It is very useful for tracking down any usage bugs.
The macro
__SDLT_VERSION
is predefined to be 2001. Programs could use it for conditional compilation if incompatibilities arise in future updates.
C++ implementations of
std::min
and
std::max
sometimes have a negative impact on performance. SDLT defines
min_val
and
max_val
that help avoid such performance penalties.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804