Developer Guide and Reference

Contents

simdoff

Specifies a block of code in the SIMD loop or SIMD-enabled function that should be executed serially, in a logical order of SIMD lanes.

Syntax

#pragma simdoff
structured-block
Arguments
None.
Description
The
simdoff
block will use a single SIMD lane to execute operations in the order of the loop iterations, or logical lanes of a SIMD-enabled function. This preserves ordering of operations in the block with respect to each other, and correlates with iteration space of the enclosing SIMD construct. The ordered
simd
block is executed in order, with respect to each SIMD lane or each loop iteration. The operations within the ordered
simd
or
simdoff
block can be re-ordered by optimizations, as long as the original execution semantics are preserved.
simdoff
blocks allow the isolation and resolution of situations prohibited from SIMD execution. This includes cross-iteration data dependencies, function calls with side effects, such as
OpenMP,
TBB and native thread synchronization primitives.
simdoff
sections are useful for resolving cross-iteration data dependencies in otherwise data-parallel computations. For example, the section may handle histogram updates as shown below:
Example
#pragma simd for (int i = 0; i < N; i++) { float amount = compute_amount(i); int cluster = compute_cluster(i); #pragma simdoff { totals[cluster] += amount; // Requires ordering to process multiple updates for the same cluster } }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804