Developer Guide and Reference

Contents

GAP Message (Diagnostic ID 30521)

Message

Assign a value to the variable(s) "%s" at the beginning of the body of the loop in line %d. This will allow the loop to be parallelized.

Advice

Check to see if you can unconditionally initialize the scalar variables at the beginning of the specified loop. If so, do the code change for such initialization (standard), or list the variables in the private clause of a parallel
pragma
(advanced). This allows the parallelizer to privatize those variables for each iteration and to parallelize the loop.
Example
Consider the following:
#define N 100000 double A[N], B[N];   void foo(int cond1, int cond2){ int i, t=7; for (i=0; i<N; i++){ if (cond1) { t = i+1; } if (cond2) { t = i-1; } A[i] = t; } }
In this case, the compiler does not parallelize the loop because it cannot privatize the variable
t
without further information. If you know that cond1 or cond2 is true, or both cond1 and cond2 are true, then you can assist the parallelizer by ensuring that any iteration that uses
t
also writes to
t
before its use in the same iteration. One of the ways to do this is to assign a value to
t
at the top of each iteration.
If you determine it is safe to do so, you can modify the program code as follows:
#define N 100000 double A[N], B[N];   void foo(int cond1, int cond2){ int i, t=7; for (i=0; i<N; i++){ t=0; if (cond1) { t = i+1; } if (cond2) { t = i-1; } A[i] = t; } }

Verify

Confirm that in the original program, any variables
read
in any iteration of the loop have been defined earlier in the same iteration.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804