Developer Guide

Contents

Details

Given
n
feature vectors
x
1
=(
x
11
,…,
x
1
p
),...,
x
n
=(
x
n
1
,…,
x
np
) of size
p
, the number of classes
K
, and a vector of class labels y=(
y
1
,…,
y
n
), where
y
i
{0, 1 ,... ,
K
-1}, the problem is to build a multi-class classifier using a two-class (binary) classifier, such as a two-class SVM.

Training Stage

The model is trained with the One-Against-One method that uses the binary classification described in [ Hsu02 ] as follows (for more references, see the Bibliography in [Hsu02]): For each pair of classes (
i
,
j
), train a binary classifier, such as SVM. The total number of such binary classifiers is
K
(
K
-1)/2.

Prediction Stage

Given a new feature vector
x
i
, the classifier determines the class to which the vector belongs.
Intel DAAL provides two methods for class label prediction:
  • Wu method. According to the algorithm 2 for computation of the class probabilities described in [ Wu04 ]. The library returns the index of the class with the largest probability.
  • Vote-based method. If the binary classifier predicts the feature vector to be in
    i
    -th class, the number of votes for the class
    i
    is increased by one, otherwise the vote is given to the
    j
    -th class. If two classes have equal numbers of votes, the class with the smallest index is selected.

Training Alternative

If for each pair of classes you already have a pre-trained model, you can use the Model Builder class to get an Intel DAAL Multi-class Classifier with these two-class classifiers (for example, two-class SVMs). After the model is built, you can proceed to the prediction stage.
For general information on using the Model Builder class, see Training and Prediction . For details on using the Model Builder class for Multi-class Classifier, see Usage of training alternative .

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804