User and Reference Guide

  • 2020
  • 10/23/2020
  • Public Content

Displaying the Current Configuration

To display the currently used Intel® PT configuration, use the
!showconfig
command. This prints a table of all the relevant model-specific registers (MSRs) that make up the Intel® PT configuration. After that, the extension prints a human-readable interpretation of that raw data, like, for example,
Tracing is enabled.
Following is an example output on a target machine with two processors:
0: kd> !showconfig Intel(R) Processor Trace configuration on processor 0 MSR address value ------------------------------------------------------- IA32_RTIT_CTL 570 0000000100002104 IA32_RTIT_STATUS 571 0000000000000002 IA32_RTIT_OUTPUT_BASE 560 0000000000001000 IA32_RTIT_OUTPUT_MASK_PTRS 561 000000000000007f IA32_RTIT_CR3_MATCH 572 0000000000000000 IA32_RTIT_ADDR0_A 580 fffff80002851c10 IA32_RTIT_ADDR0_B 581 fffff80002851e81 IA32_RTIT_ADDR1_A 582 0000000000000000 IA32_RTIT_ADDR1_B 583 0000000000000000 Tracing is disabled. CR3 filtering is disabled. IP filter configuration: 0: fffff80002851c10 - fffff80002851e81 enable 1: 0000000000000000 - 0000000000000000 unused Table of Physical Addresses (ToPA) output method used. Table of Physical Addresses (ToPA) output configuration details: .-- TABLE 0000000000001000 `-- REGION base 0000000000006000, size 8K, flags ---- STOP Intel(R) Processor Trace configuration on processor 1 MSR address value ------------------------------------------------------- IA32_RTIT_CTL 570 0000000100002104 IA32_RTIT_STATUS 571 0000000000000002 IA32_RTIT_OUTPUT_BASE 560 0000000000002000 IA32_RTIT_OUTPUT_MASK_PTRS 561 000000000000007f IA32_RTIT_CR3_MATCH 572 0000000000000000 IA32_RTIT_ADDR0_A 580 fffff80002851c10 IA32_RTIT_ADDR0_B 581 fffff80002851e81 IA32_RTIT_ADDR1_A 582 0000000000000000 IA32_RTIT_ADDR1_B 583 0000000000000000 Tracing is disabled. CR3 filtering is disabled. IP filter configuration: 0: fffff80002851c10 - fffff80002851e81 enable 1: 0000000000000000 - 0000000000000000 unused Table of Physical Addresses (ToPA) output method used. Table of Physical Addresses (ToPA) output configuration details: .-- TABLE 0000000000002000 `-- REGION base 0000000000008000, size 8K, flags ---- STOP

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804