User and Reference Guide

  • 2020
  • 10/23/2020
  • Public Content

Extension Commands for Decoding Intel® Processor Trace

After code execution is traced, the extension provides the
command to download the trace, decode it, and display it. The
!decode /info
command displays the decoded amount of instructions. To display the reconstructed execution flow and navigate it, you can invoke
with no, one, or two range specifiers. If you do not provide the
range specifier, the entire decoded trace is displayed. With two numbers, only the instructions in that decode range are displayed; for example,
!decode 15 23
displays decoded instructions 15 through 23. If you specify only one number, the first or last number of decode lines are printed, depending on whether the number is positive or negative. For example,
!decode 5
displays the first five lines, and
!decode -12
displays the last twelve lines.
In general, the
command displays the disassembly of all the decoded instructions. If symbols are available, addresses are displayed with symbol decoration. If sources are available and you want the trace decode to be annotated with source lines that were executed, you can set the
option. If you only want source lines to be displayed, the
option suppresses the display of instruction disassembly lines.
When source line annotation is requested, the beginning of the source line shows the source location as
[<source file name>:<line number>]
; for example,
. If debugger markup language (DML) is supported and enabled, these source locations are displayed as links – clicking such a link opens the source file and scrolls to the respective line.
To show timestamp information in decoded output, use the
option. See section Timestamps for information about enabling Intel Processor Trace timestamp packets. Additionally, you can specify the source of the base frequency for decoding the timestamps by selecting one of the following:
  • /cpuid_0x15_eax
    - the Core Crystal Clock frequency value returned by the
    instruction is used for decoding. You have to specify both options for this to work.
  • /nom_freq
    - the nominal frequency specified in the model-specific register
    is used for decoding.
!decode [/info] [/src] [/srconly] [/symbols] [/timestamps] [/offline] [/topa] [/family <expr>] [/model <expr>] [/stepping <expr>] [/cpuid_0x15_eax <expr>] [/cpuid_0x15_ebx <expr>] [/output_base <expr>] [/output_mask <expr>] [<n>] [<start>] [<end>] /info - Get decode information /src - Interleave source lines (if available) /srconly - Show only source lines (if available) /symbols - Show export symbol names (if available) /timestamps - Show timestamps (if available) <n> - Number of lines to display; if positive print first n lines, if negative print last n lines (cannot be used together with <start> and <end> ) (space-delimited, base 10) <start> - Start of line number range (use together with <end> ) (space-delimited, base 10) <end> - End of line number range (use together with <start> ) (space-delimited, base 10) /family <expr> - Extended CPU Family ID to be used during decode (space-delimited) /model <expr> - Extended CPU Model ID to be used during decode (space-delimited) /stepping <expr> - CPU Stepping ID to be used during decode (space-delimited) /cpuid_0x15_eax <expr> - CTC frequency configuration(cpuid_eax(0x15, 0)) (space-delimited) /cpuid_0x15_ebx <expr> - CTC frequency configuration(cpuid_ebx(0x15, 0)) (space-delimited) /offline - Decode Intel(R) Processor Trace data without connection to a target. (Following values have to be specified) /output_base <expr> - Start address of available buffer (MSR 0x560) (space-delimited) /output_mask <expr> - Size of available buffer (MSR 0x561) (space-delimited) /topa - Specify ToPA output config option (single range is default) Decode Intel(R) Processor Trace and display reconstructed execution history

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804