User and Reference Guide

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  • 07/29/2020
  • Public Content


Enabling Timestamps in Intel® PT Output

You can configure Intel® Processor Trace (Intel® PT) to include timestamps into its output by invoking the command
!enabletimestamps <options>
!enabletimestamps [/tsc] [/mtc] [/cyc] [/here] [/mtcfreq <expr>] [/cycthres <expr>] /tsc - Enable TSC(Time Stamp Counter) /mtc - Enable MTC(Mini Time Counter) /mtcfreq <expr> - MTCFrequency value 0 - max frequency possible options shown if parameter is not provided. (For examlpe b01001 allow [0 and 3]) (space-delimited) /cyc - Enable Cycle-Accurate Mode /cycthres <expr> - CycThreshold value 0 - no threshold CycThresh>0, CYC packets are generated only after a minimum number of cycles have passed since the last CYC packet possible options shown if parameter is not provided. (For example b01111 allow [0,1,2,3]) (space-delimited) /here - Enable on the currently selected processor only Enable timestamps (only JTAG connection)

Types of Timestamp Packets in Intel® PT

There are three types of Intel PT timestamp packets that Intel® CPUs can generate:
  1. Time Stamp Counter (TSC) packets contain the approximate wall-clock time of the event that generated the packet. TSC packets are generated by events such as packet generation enable and sleep state wake. TSC packets do not precisely indicate the time of any control flow packets; however, all preceding packets represent instructions that executed before the indicated TSC time, and all subsequent packets represent instructions that executed after the TSC time. There is not a precise IP to which to bind the TSC packet. The value of a TSC packet is the current TSC value as returned by the
    You can enable TSC packets by passing the option
    to the
  2. Mini Time Counter (MTC) packets provide a periodic indication of the wall-clock time. This allows the decoder to keep track of how much wall-clock time has elapsed since the last TSC packet was sent, by keeping track of how many MTC packets were sent and what their value was. As their payload, MTC packets contain the Common Timestamp Copy (CTC). The CTC is an 8-bit range taken from the value of the core crystal clock, starting from the
    -th bit. Intel PT sends an MTC packet every time the value of CTC changes; therefore, the value of
    controls the frequency of MTC packets.
    You can enable MTC packets by passing the option
    to the
    command. Additionally, you can pass the option
    to specify the frequency of the MTC packets. The frequency value
    means that an MTC packet is sent every time bit
    of the core crystal clock changes. The value 0 means that Intel PT sends an MTC packet every tick of the core crystal clock.
  3. Cycle Count (CYC) packets provide the number of core clocks that have passed since the last CYC packet. CYC can be configured to be sent in every cycle in which an eligible packet is generated, or software can opt to use a threshold to limit the number of CYC packets. A CYC packet precedes other packets generated in the same cycle and provides the precise cycle time of the packets that follow.
    You can enable CYC packets by passing the option
    to the
    command. Additionally, you can pass the option
    to specify the threshold for CYC packet generation. The threshold value
    = 0 means that no threshold is in use, and a CYC packet will be generated in any cycle in which any CYC-eligible packet is generated. A threshold value
    > 0 means that CYC packets are generated only after at least
    cycles have passed since the last CYC packet.
For more information about Intel PT packets, see the
Intel® 64 and IA-32 Architectures Software Developer's Manual
, volume 3C.
You can enable and configure Intel PT packets independently of each other, but you have to enable at least one type of packets to enable timestamps.

Choosing Your Timestamp Packet Configuration

Timestamps consume the Intel PT buffer even when no instruction trace is recorded. You have to choose your timestamp packet configuration taking into account the buffer size and the active filters.
Note the following points when choosing your configuration:
  • Enabling only Time Stamp Counter (TSC) packets means that you do not have a precise indication of instruction trace timing.
  • Enabling Mini Time Counter (MTC) and Cycle Count (CYC) packets, but not TSC packets, gives you timing data relative to 0. Enabling TSC packets gives you the ability to analyze execution with other timing sources.
  • Enabling MTC and CYC packets is key to getting precise timing information. Use
    /mtcfreq 0
    /cycthres 0
    to get the maximum level of precision.
  • The decoder uses the combination of MTC and CYC packets to track instruction execution time. Increase the MTC frequency and decrease the CYC threshold to find the best combination to fit your needs. Consider the following:
    • MTC packets are periodic and based on the core crystal clock. Using the maximum frequency value
      /mtcfreq 0
      allows the decoder to identify the timing of small sequences of instructions. Reducing the frequency reduces accuracy.
    • CYC packets rely on the processor core clock, which can experience delays depending on the P-State and thermal conditions. Increasing the threshold for CYC packets reduces the number of CYC packets stored in the Intel PT buffer at the cost of reduced accuracy.

Disabling Timestamp Packets in Intel® PT

To drop the current timestamp configuration of Intel PT, invoke the
!disabletimestamps [/here] /here - Disable on the currently selected processor only Disable timestamps

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804