• XX.XX
  • 09/30/2019
  • Public Content

Get Started with Intel® Integrated Performance Primitives Cryptography
2020
for
Windows* OS

Intel® Integrated Performance Primitives (Intel® IPP) Cryptography is a software library that provides a broad range of secure and efficient cryptographic algorithm implementations.
Intel IPP Cryptography is available as part of the following suite
s
:
The library is also available as a standalone package under the Community Licensing program.
Please note that Intel IPP Cryptography is an export-controlled product, and must be obtained through a special request process. See Where do I download the Intel® IPP Cryptography libraries? for detailed instructions.

Prerequisites

Set Environment Variables
After installing Intel IPP Cryptography, set the
PATH
,
LIB
, and
INCLUDE
environment variables by running the script appropriate to your target platform architecture. The scripts are available in
<install dir>
\
ippcp
\
bin
.
By default, the
<install dir>
is
C:\Program files (x86)\IntelSWTools\compilers_and_libraries_2020.x.xxx\
<target_os>
Configure Your IDE Environment to Link with Intel IPP Cryptography
To configure your Microsoft* Visual Studio* development system for linking with the Intel IPP Cryptography library, follow the steps below. Though some versions of the Visual Studio* IDE may vary slightly in the menu items mentioned below, the fundamental configuring steps are applicable to all these versions.
  1. In Solution Explorer, right-click your project and click
    Properties
    .
  2. Select
    Configuration Properties
    >
    VC++ Directories
    and set the following from the
    Select directories for
    drop down menu:
    • Include Files
      menu item, and then type in the directory for the Intel IPP Cryptography include files (default is
      <install_dir>
      \ippcp\include
      )
    • Library Files
      menu item, and then type in the directory for the Intel IPP Cryptography library files (default is
      <install_dir>
      \ippcp\lib\<arch>
      )
    • Executable Files
      menu item, and then type in the directory for the Intel IPP Cryptography executable files (default is
      <install_dir>
      \redist\<arch>\ippcp
      )

Build and Run Your First Intel® IPP Cryptography Application

The code example below represents a short application to help you get started with Intel IPP Cryptography:
#include "ippcp.h" #include <stdio.h> #define ippCPUID_MMX 0x00000001 /* Intel(R) Architecture MMX(TM) technology */ #define ippCPUID_SSE 0x00000002 /* Intel(R) Streaming SIMD Extensions */ #define ippCPUID_SSE2 0x00000004 /* Intel(R) Streaming SIMD Extensions 2 */ #define ippCPUID_SSE3 0x00000008 /* Intel(R) Streaming SIMD Extensions 3 */ #define ippCPUID_SSSE3 0x00000010 /* Supplemental Streaming SIMD Extensions 3 */ #define ippCPUID_MOVBE 0x00000020 /* The processor supports the MOVBE instruction */ #define ippCPUID_SSE41 0x00000040 /* Intel(R) Streaming SIMD Extensions 4.1 */ #define ippCPUID_SSE42 0x00000080 /* Intel(R) Streaming SIMD Extensions 4.2 */ #define ippCPUID_AVX 0x00000100 /* Intel(R) Advanced Vector Extensions (Intel(R) AVX) */ #define ippAVX_ENABLEDBYOS 0x00000200 /* The operating system supports Intel AVX */ #define ippCPUID_AES 0x00000400 /* Intel(R) AES New Instructions (Intel(R) AES-NI) */ #define ippCPUID_CLMUL 0x00000800 /* PCLMULQDQ instruction */ #define ippCPUID_ABR 0x00001000 /* Reserved */ #define ippCPUID_RDRAND 0x00002000 /* Read Random Number instructions */ #define ippCPUID_F16C 0x00004000 /* Float16 instructions */ #define ippCPUID_AVX2 0x00008000 /* Intel(R) Advanced Vector Extensions 2 */ #define ippCPUID_ADCOX 0x00010000 /* ADCX and ADOX instructions */ #define ippCPUID_RDSEED 0x00020000 /* The RDSEED instruction */ #define ippCPUID_PREFETCHW 0x00040000 /* The PREFETCHW instruction */ #define ippCPUID_SHA 0x00080000 /* Intel(R) SHA Extensions */ #define ippCPUID_AVX512F 0x00100000 /* Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512) Foundation instructions */ #define ippCPUID_AVX512CD 0x00200000 /* Intel AVX-512 Conflict Detection instructions */ #define ippCPUID_AVX512ER 0x00400000 /* Intel AVX-512 Exponential & Reciprocal instructions */ #define ippCPUID_AVX512PF 0x00800000 /* Intel AVX-512 Prefetch instructions */ #define ippCPUID_AVX512BW 0x01000000 /* Intel AVX-512 Byte & Word instructions */ #define ippCPUID_AVX512DQ 0x02000000 /* Intel AVX-512 DWord & QWord instructions */ #define ippCPUID_AVX512VL 0x04000000 /* Intel AVX-512 Vector Length extensions */ #define ippCPUID_AVX512VBMI 0x08000000 /* Intel AVX-512 Vector Bit Manipulation instructions */ #define ippCPUID_MPX 0x10000000 /* Intel(R) Memory Protection Extensions */ #define ippCPUID_AVX512_4FMADDPS 0x20000000 /* Intel AVX-512 DL floating-point single precision */ #define ippCPUID_AVX512_4VNNIW 0x40000000 /* Intel AVX-512 DL enhanced word variable precision */ #define ippCPUID_KNC 0x80000000 /* Intel(R) Xeon Phi(TM) Coprocessor */ int main(int argc, char* argv[]) { const IppLibraryVersion *lib; IppStatus status; Ipp64u mask, emask; /* Get Intel IPP Cryptography library version info */ lib = ippcpGetLibVersion(); printf("%s %s\n", lib->Name, lib->Version); /* Get CPU features and features enabled with selected library level */ status = ippcpGetCpuFeatures( &mask ); if( ippStsNoErr == status ) { emask = ippcpGetEnabledCpuFeatures(); printf("Features supported by CPU\tby Intel(R) Integrated Performance Primitives Cryptography\n"); printf("-----------------------------------------\n"); printf(" ippCPUID_MMX = "); printf("%c\t%c\t",( mask & ippCPUID_MMX ) ? 'Y':'N',( emask & ippCPUID_MMX ) ? 'Y':'N'); printf("Intel(R) Architecture MMX technology supported\n"); printf(" ippCPUID_SSE = "); printf("%c\t%c\t",( mask & ippCPUID_SSE ) ? 'Y':'N',( emask & ippCPUID_SSE ) ? 'Y':'N'); printf("Intel(R) Streaming SIMD Extensions\n"); printf(" ippCPUID_SSE2 = "); printf("%c\t%c\t",( mask & ippCPUID_SSE2 ) ? 'Y':'N',( emask & ippCPUID_SSE2 ) ? 'Y':'N'); printf("Intel(R) Streaming SIMD Extensions 2\n"); printf(" ippCPUID_SSE3 = "); printf("%c\t%c\t",( mask & ippCPUID_SSE3 ) ? 'Y':'N',( emask & ippCPUID_SSE3 ) ? 'Y':'N'); printf("Intel(R) Streaming SIMD Extensions 3\n"); printf(" ippCPUID_SSSE3 = "); printf("%c\t%c\t",( mask & ippCPUID_SSSE3 ) ? 'Y':'N',( emask & ippCPUID_SSSE3 ) ? 'Y':'N'); printf("Supplemental Streaming SIMD Extensions 3\n"); printf(" ippCPUID_MOVBE = "); printf("%c\t%c\t",( mask & ippCPUID_MOVBE ) ? 'Y':'N',( emask & ippCPUID_MOVBE ) ? 'Y':'N'); printf("The processor supports MOVBE instruction\n"); printf(" ippCPUID_SSE41 = "); printf("%c\t%c\t",( mask & ippCPUID_SSE41 ) ? 'Y':'N',( emask & ippCPUID_SSE41 ) ? 'Y':'N'); printf("Intel(R) Streaming SIMD Extensions 4.1\n"); printf(" ippCPUID_SSE42 = "); printf("%c\t%c\t",( mask & ippCPUID_SSE42 ) ? 'Y':'N',( emask & ippCPUID_SSE42 ) ? 'Y':'N'); printf("Intel(R) Streaming SIMD Extensions 4.2\n"); printf(" ippCPUID_AVX = "); printf("%c\t%c\t",( mask & ippCPUID_AVX ) ? 'Y':'N',( emask & ippCPUID_AVX ) ? 'Y':'N'); printf("Intel(R) Advanced Vector Extensions (Intel(R) AVX) instruction set\n"); printf(" ippAVX_ENABLEDBYOS = "); printf("%c\t%c\t",( mask & ippAVX_ENABLEDBYOS ) ? 'Y':'N',( emask & ippAVX_ENABLEDBYOS ) ? 'Y':'N'); printf("The operating system supports Intel(R) AVX\n"); printf(" ippCPUID_AES = "); printf("%c\t%c\t",( mask & ippCPUID_AES ) ? 'Y':'N',( emask & ippCPUID_AES ) ? 'Y':'N'); printf("Intel(R) AES instruction\n"); printf(" ippCPUID_SHA = "); printf("%c\t%c\t",( mask & ippCPUID_SHA ) ? 'Y':'N',( emask & ippCPUID_SHA ) ? 'Y':'N'); printf("Intel(R) SHA new instructions\n"); printf(" ippCPUID_CLMUL = "); printf("%c\t%c\t",( mask & ippCPUID_CLMUL ) ? 'Y':'N',( emask & ippCPUID_CLMUL ) ? 'Y':'N'); printf("PCLMULQDQ instruction\n"); printf(" ippCPUID_RDRAND = "); printf("%c\t%c\t",( mask & ippCPUID_RDRAND ) ? 'Y':'N',( emask & ippCPUID_RDRAND ) ? 'Y':'N'); printf("Read Random Number instructions\n"); printf(" ippCPUID_F16C = "); printf("%c\t%c\t",( mask & ippCPUID_F16C ) ? 'Y':'N',( emask & ippCPUID_F16C ) ? 'Y':'N'); printf("Float16 instructions\n"); printf(" ippCPUID_AVX2 = "); printf("%c\t%c\t",( mask & ippCPUID_AVX2 ) ? 'Y':'N',( emask & ippCPUID_AVX2 ) ? 'Y':'N'); printf("Intel(R) Advanced Vector Extensions 2 instruction set\n"); printf(" ippCPUID_AVX512F = "); printf("%c\t%c\t",( mask & ippCPUID_AVX512F ) ? 'Y':'N',( emask & ippCPUID_AVX512F ) ? 'Y':'N'); printf("Intel(R) Advanced Vector Extensions 512 Foundation instruction set\n"); printf(" ippCPUID_AVX512CD = "); printf("%c\t%c\t",( mask & ippCPUID_AVX512CD ) ? 'Y':'N',( emask & ippCPUID_AVX512CD ) ? 'Y':'N'); printf("Intel(R) Advanced Vector Extensions 512 Conflict Detection instruction set\n"); printf(" ippCPUID_AVX512ER = "); printf("%c\t%c\t",( mask & ippCPUID_AVX512ER ) ? 'Y':'N',( emask & ippCPUID_AVX512ER ) ? 'Y':'N'); printf("Intel(R) Advanced Vector Extensions 512 Exponential & Reciprocal instruction set\n"); printf(" ippCPUID_ADCOX = "); printf("%c\t%c\t",( mask & ippCPUID_ADCOX ) ? 'Y':'N',( emask & ippCPUID_ADCOX ) ? 'Y':'N'); printf("ADCX and ADOX instructions\n"); printf(" ippCPUID_RDSEED = "); printf("%c\t%c\t",( mask & ippCPUID_RDSEED ) ? 'Y':'N',( emask & ippCPUID_RDSEED ) ? 'Y':'N'); printf("The RDSEED instruction\n"); printf(" ippCPUID_PREFETCHW = "); printf("%c\t%c\t",( mask & ippCPUID_PREFETCHW ) ? 'Y':'N',( emask & ippCPUID_PREFETCHW ) ? 'Y':'N'); printf("The PREFETCHW instruction\n"); printf(" ippCPUID_KNC = "); printf("%c\t%c\t",( mask & ippCPUID_KNC ) ? 'Y':'N',( emask & ippCPUID_KNC ) ? 'Y':'N'); printf("Intel(R) Xeon Phi(TM) Coprocessor instruction set\n"); } return 0; }
This application consists of two sections:
  1. Get the library layer name and version.
  2. Show the hardware optimizations used by the selected library layer and supported by CPU.
On Windows* OS, Intel IPP Cryptography applications are significantly easier to build with Microsoft* Visual Studio*. To build the code example above, follow the steps:
  1. Start Microsoft* Visual Studio* and create an empty C++ project.
  2. Add a new c file and paste the code into it.
  3. Set the include directories and the linking model as described in Configure Your IDE Environment to Link with Intel IPP Cryptography.
  4. Compile and run the application.

Training and Documentation

To learn more about the product, see the following
online
resources:
Document
Description
Provides detailed guidance on Intel IPP Cryptography library configuration, development environment, and linkage modes. A Japanese version is available in the downloadable studio documentation bundle at https://software.intel.com/en-us/articles/download-documentation-intel-parallel-studio-xe-current-previous.
Contains detailed descriptions of the Intel IPP Cryptography functions.
Intel® IPP product page. See this page for support and online documentation for the Intel IPP library in general.
You can also download an offline version of the documentation from:

Notices and Disclaimers

Intel, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
© Intel Corporation.
This software and the related documents are Intel copyrighted materials, and your use of them is governed by the express license under which they were provided to you (
License
). Unless the License provides otherwise, you may not use, modify, copy, publish, distribute, disclose or transmit this software or the related documents without Intel's prior written permission.
This software and the related documents are provided as is, with no express or implied warranties, other than those that are expressly stated in the License.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804