• Intel® Graphics Performance Analyzers 2019 R4
  • 12/20/2019
  • Public Content
Contents

Set 7

EU FPU0 Binary Instruction
EU FPU0 Binary Instruction : The percentage of time in which execution units were actively processing binary instructions on FPU0.
EU FPU0 Hybrid Instruction
EU FPU0 Hybrid Instruction : The percentage of time in which execution units were actively processing hybrid instructions on FPU0.
EU FPU0 Move Instruction
EU FPU0 Move Instruction : The percentage of time in which execution units were actively processing move instructions on FPU0.
EU FPU0 Ternary Instruction
EU FPU0 Ternary Instruction : The percentage of time in which execution units were actively processing ternary instructions on FPU0.
EU FPU1 Binary Instruction
EU FPU1 Binary Instruction : The percentage of time in which execution units were actively processing binary instructions on FPU1.
EU FPU1 Hybrid Instruction
EU FPU1 Hybrid Instruction : The percentage of time in which execution units were actively processing hybrid instructions on FPU1.
EU FPU1 Move Instruction
EU FPU1 Move Instruction : The percentage of time in which execution units were actively processing move instructions on FPU1.
EU FPU1 Ternary Instruction
EU FPU1 Ternary Instruction : The percentage of time in which execution units were actively processing ternary instructions on FPU1.
L3 Accesses
L3 Accesses : The total number of L3 accesses from all entities.
L3 Bank 00 Accesses
L3 Bank 00 Accesses : The total number of accesses to L3 Bank 00.
L3 Bank 00 IC Accesses
L3 Bank 00 IC Accesses : The total number of accesses to L3 Bank 00 from IC cache.
L3 Bank 00 IC Hits
L3 Bank 00 IC Hits : The total number of hits in L3 Bank 00 from IC cache.
L3 Bank 01 Accesses
L3 Bank 01 Accesses : The total number of accesses to L3 Bank 01.
L3 Bank 02 Accesses
L3 Bank 02 Accesses : The total number of accesses to L3 Bank 02.
L3 Bank 03 Accesses
L3 Bank 03 Accesses : The total number of accesses to L3 Bank 03.
L3 Bank 10 Accesses
L3 Bank 10 Accesses : The total number of accesses to L3 Bank 10.
L3 Bank 10 IC Accesses
L3 Bank 10 IC Accesses : The total number of accesses to L3 Bank 10 from IC cache.
L3 Bank 10 IC Hits
L3 Bank 10 IC Hits : The total number of hits in L3 Bank 10 from IC cache.
L3 Bank 11 Accesses
L3 Bank 11 Accesses : The total number of accesses to L3 Bank 11.
L3 Bank 12 Accesses
L3 Bank 12 Accesses : The total number of accesses to L3 Bank 12.
L3 Bank 13 Accesses
L3 Bank 13 Accesses : The total number of accesses to L3 Bank 13.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.