User Guide

  • 2020
  • 09/09/2020
  • Public Content

Key Terminology

: A process during which the
Intel Inspector
performs collection and finalization.
code location
: A fact the
Intel Inspector
observes at a source code location, such as a
code location. Previously called an
: A process during which the
Intel Inspector
executes an application, identifies issues that may need handling, and collects those issues in a result.
false positive
: A reported error that is not an error.
: A process during which the
Intel Inspector
uses debug information from binary files to convert symbol information into filenames and line numbers, performs duplicate elimination (if requested), and forms problem sets.
: One or more occurrences of a detected issue, such as an uninitialized memory access. Multiple occurrences have the same call stack but a different thread or timestamp. You can view information for a problem as well as for each occurrence.
problem breakpoint
: A breakpoint that halts execution when a memory or threading analysis detects a problem.
In a Linux* debugger, a problem breakpoint is indicated by display of source line information, a unique problem breakpoint ID, and a short problem description.
problem set
: A group of problems with a common problem type and a shared code location that might share a common solution, such as a problem set resulting from deallocating an object too early during application execution. You can view problem sets only after analysis is complete.
: A compiled application; a collection of configurable attributes, including suppression rules and search directories; and a container for analysis results.
: A collection of issues that may need handling.
: An
Intel Inspector
productivity enhancement feature you can use to not collect result data that matches a rule you define.
: An application the
Intel Inspector
inspects for errors.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804