User Guide

  • 2020
  • 05/04/2020
  • Public Content
Contents

Invalid Partial Memory Access

Occurs when a read or write instruction references a block (2-bytes or more) of memory where part of the block is logically invalid.
Problem type: Invalid partial memory access
Problem type: Invalid memory access (Write)
ID
Code Location
Description
1
Allocation site
If present, represents the location and associated call stack from which the memory block adjacent to the offending address was allocated.
2
Deallocation site
If present, represents the location and associated call stack from which the memory block containing the offending address was deallocated.
The deallocation makes the access to the offending memory address logically invalid.
3
Read or Write
Represents the instruction and associated call stack responsible for the partial invalid access.
If no allocation or deallocation is associated with this problem, the memory address might be one of the following:
  • Logically invalid stack space (below the current stack pointer value)
  • Memory that is physically not allocated to the process
The offset, if shown in the
Code Locations
pane, represents the byte offset into the allocated buffer where the
Invalid partial memory access
occurred.
struct tally {    int num;    char count; }; struct tally *pCurrent = (struct tally *)malloc(5); // incorrect size allocated struct tally *pRoot = (struct tally *)malloc(sizeof(struct tally)); pCurrent->num = 1; pCurrent->count = 1; *pRoot = *pCurrent; // will result in partial invalid read
Different compilers and optimization levels can produce different assembly for block copies of memory. Depending on the generated assembly, this example might produce an invalid memory access problem.
Possible Correction Strategies
The typical cause of an invalid partial memory access problem is a miscalculation of the required size of an object. Determine the correct size for object creation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804