User Guide

  • 2020
  • 05/04/2020
  • Public Content
Contents

Uninitialized Partial Memory Access

Occurs when a read instruction references a block (2-bytes or more) of memory where part of the block is uninitialized.
Problem type: Uninitialized partial memory access
ID
Code Location
Description
1
Allocation site
If present, represents the location and associated call stack from which the memory block containing the offending address was allocated.
2
Read
Represents the instruction and associated call stack responsible for the partial uninitialized access.
If no allocation or deallocation is associated with this problem, the memory address might be in stack space.
The offset, if shown in the
Code Locations
pane, represents the byte offset into the allocated buffer where the
Uninitialized partial memory access
occurred.
struct person {     unsigned char age;     char firstInitial;     char middleInitial;     char lastInitial; }; struct person *p1, *p2; p1 = (struct person*) malloc(sizeof(struct person)); p2 = (struct person*) malloc(sizeof(struct person)); p1->firstInitial = 'c'; p1->lastInitial = 'o'; *p2 = *p1; // will result in partial uninitialized read
type node character data1 character data2 end type node ! Variables type(node) :: a, b a%data1 = "a" b = a
Buffers created by system calls linking processes to shared memory are flagged as allocated memory, which means the
Intel Inspector
does not report an
Uninitialized partial memory access
on these buffers.
Possible Correction Strategies
Determine the correct initialization for the memory being accessed.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804