User Guide

  • 2020
  • 05/04/2020
  • Public Content
Contents

Pane: Timeline

Pane position in window
To access this
Intel Inspector
pane: Click the
Summary
button on the
Navigation
toolbar. Use this pane on the
Summary
window to graphically visualize the relationship between threads and the code locations for the problem occurrences displayed in the
Code Locations
pane.
Use This
To Do This
Pane controls
  • Show code location information in text form (hover the mouse pointer over a Dynamic event icon 
								or Dynamic event icon 
								marker).
    There is a marker for every code location in the problem occurrence displayed in the
    Code Locations
    pane. If a marker is hidden behind another, the
    Intel Inspector
    shows text information for both the shown and hidden code locations.
  • Show/hide this pane (click Pane toggle icon or ).
Thread (blue) bars
  • Review the number of threads used during application execution.
  • Review relative thread duration.
  • Distinguish a thread with a code location in the
    Code Locations
    pane (thick bar) from a thread without such a code location (thin bar).
  • Identify the name of a thread with a code location in the
    Code Locations
    pane.
    Intel Inspector
    tries to provide meaningful thread names in the following forms:
    • Thread ID
    • And thread name or function called to start the thread
Dynamic event icon 
						marker
Identify the thread with the code location highlighted in the
Code Locations
pane.
Dynamic event icon 
						  marker(s)
Identify the thread with code locations not highlighted in the
Code Locations
pane.
Pane border
Resize the pane (drag).
Context menu
View Source
- Display a
Sources
window focused on the selected problem occurrence.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804