• 07/14/2017
  • Public Content

Imaging Specifications

The Imaging Processing Unit (IPU) consists of the Processing Subsystem (PS) and the Input Subsystem (IS). The Processing Subsystem is an advanced Image Signal processor (ISP). The Input Subsystem contains the MIPI CSI2 controllers. The IPU interfaces with the CMOS image sensors in the camera module through the IS and processes still and video frames in the PS.
Number of Cameras Supported
  • The IPU can support a maximum of four cameras
  • Typical expected usage is one primary camera and one secondary camera
  • Allocating four cameras between world and user-facing views is ultimately at the designer’s discretion
Simultaneous Acquisition
  • All cameras can be active at the same time
  • The IS saves streams to memory for off line processing and for one primary camera
  • On-the-fly processing is also supported

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804