Module to Expansion Board Connectors
Module electrostatic discharge
ESD testing is performed at the system level, where the module is connected to an expansion board, and not at the module connectors. See the Mechanical and Environmental topic for more ESD information.
J6 connector interface signals
Pin | Signal Name | Usage | Description |
36 | +VDD1 | Output | System 1.8 V |
30 | +VDD3 | Output | System 3.3 V |
41 | +V5P0V_VCONN | Input | Power for USB3.0 CC pins for VCONN-powered accessory. |
40 | CHRG_INT_N | Input | General purpose input/output for the expansion board charger’s interrupt pin, active low. Allows charger to interrupt host to report charger device status and faults. Connected to GPIO_19. |
35 | CHRG_EN_N | Output | General purpose input/output for the expansion board charger’s enable pin, active low. See Battery Path for details. Connected to GPIO_15. |
43 | CODEC_MCLK | Output | MCLK for Master Mode operation for I2S audio |
16 | ISH_I2C_0_SCL see Note | Output | Integrated sensor hub port 0 I2C clock (open collector) Note: I2C port 0 remapped to I2C port 5 in BIOS |
18 | ISH_I2C_0_SDA see Note | Input/Output | Integrated sensor hub port 0 I2C data (open collector) Note: I2C port 0 remapped to I2C port 5 in BIOS |
21 | ISH_I2C_1_SCL see Note | Output | Integrated sensor hub port 1 I2C clock (open collector) Note: I2C port 1 remapped to I2C port 6 in BIOS |
23 | ISH_I2C_1_SDA see Note | Input/Output | Integrated sensor hub port 1 I2C data (open collector) Note: I2C port 1 remapped to I2C port 6 in BIOS |
46 | HDMI_CLK_DN | Output | HDMI* clock negative |
44 | HDMI_CLK_DP | Output | HDMI* clock positive |
68 | DDI1_CTRL_CLK | Output | HDMI* I2C clock |
70 | DDI1_CTRL_DAT | Input/Output | HDMI* I2C data |
62 | HDMI_TX_0_DN | Output | HDMI* data lane 0 negative |
58 | HDMI_TX_1_DN | Output | HDMI* data lane 1 negative |
50 | HDMI_TX_2_DN | Output | HDMI* data lane 2 negative |
64 | HDMI_TX_0_DP | Output | HDMI* data lane 0 positive |
56 | HDMI_TX_1_DP | Input/Output | HDMI* data lane 1 positive |
52 | HDMI_TX_2_DP | Output | HDMI* data lane 2 positive |
74 | UART2_CTS | Input |
UART port 2 clear to send. UART port 2 is used as a debug port for BIOS messages during boot.
|
76 | UART2_RTS | Output | UART port 2 ready to send. UART port 2 is used as a debug port for BIOS messages during boot. |
80 | UART2_RXD | Input | UART port 2 receive data. UART port 2 is used as a debug port for BIOS messages during boot. |
78 | UART2_TXD | Output | UART port 2 transmit data. UART port 2 is used as a debug port for BIOS messages during boot. Pin includes hardware strapping functionality for DNX boot. |
4, 10, 19, 42, 48, 54, 60, 66, 72, 73, 82, 86, 96, 98, 100 | GND | Ground | System ground |
39 | I2S_1_CLK | Input/Output | I2S bit clock. Supplied by the module in master mode and serves as an input in slave mode. |
45 | I2S_1_FS | Output | I2S frame sync |
47 | I2S_1_RXD | Input | I2S receive data |
49 | I2S_1_TXD | Output | I2S transmit data |
94 | GPIO_22 | Input/Output | General purpose input/output |
1 | PWM_0 | Output | Programmable pulse width modulator port 0 |
3 | PWM_1 | Output | Programmable pulse width modulator port 1 |
22 | PWM_2 | Output | Programmable pulse width modulator port 2 |
24 | PWM_3 | Output | Programmable pulse width modulator port 3 |
65 | HPD_SRC | Input | General purpose input/output for HDMI cable hot plug detect. Instantiates a start-up communication between source and sink HDMI devices. Connected to GPIO_200. |
84 | BTN_N | Input | Connected to general purpose button on the expansion board. Connected to GPIO_17. |
57 | I2C_0_SCL | Output | I2C port 0 clock |
95 | I2C_0_SDA | Input/Output | I2C port 0 data |
25 | ISH_GPIO_0 see Note | Input/Output | General purpose input/output 0 |
27 | ISH_GPIO_1 see Note | Input/Output | General purpose input/output 1 |
32 | ISH_GPIO_2 see Note | Input/Output | General purpose input/output 2 |
34 | ISH_GPIO_3 see Note | Input/Output | General purpose input/output 3 |
29 | ISH_GPIO_4 see Note | Input/Output | General purpose input/output 4 |
38 | ISH_GPIO_5 see Note | Input/Output | General purpose input/output 5 |
31 |
ISH_GPIO_6 see Note | Input/Output | General purpose input/output 6 |
71 | CLK_19P2M | Output | 19.2 MHz clock |
69 | OTG_EN | Output | General purpose input/output controlled by PMIC to enable the module to power a USB OTG device |
9 | PMIC_PWRBTN_N | Input | System power/sleep button input to PMIC; active low. |
33 | PMIC_PWRGOOD | Outpu | Notification to system that all cold boot voltage rails to power the system have ramped up. Transitions high when module rails are within specification. |
13 | PMIC_RESET_N | Input | Notification to system that PMIC will respond to commands. When asserted, the PMIC will not respond to SoC commands via I2C or SVID because of the PMIC being either in standby or because a TLP is running. This is an active low signal. |
79 | SDCARD_CD_N | Input | SD card detect. Active low when a card is present, pulled high with internal pull-up when card is not present. |
75 | SDCARD_CLK | Output |
SD card clock
|
89 | SDCARD_CMD | Input/Output |
SD card command is used for card initialization and transfer of commands.
|
81 | SDCARD_D0 | Input/Output |
SD card data 0. By default, during power up or reset, only data 0 is used for data transfer.
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83 | SDCARD_D1 | Input/Output |
SD card data 1
|
85 | SDCARD_D2 | Input/Output |
SD card data 2
|
87 | SDCARD_D3 | Input/Output |
SD card data 3
|
77 | SDCARD_LVL_CLK_FB | Input |
SD card clock feedback for aligning the SDIO data from the level shifter on-board the expansion board via the controller. There is a loopback through the SD card level shifter that drives this pin.
|
90 | SDCARD_LVL_CMD_DIR | Output |
SD card command direction indicates whether host is transmitting or receiving over the command pin.
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67 | SDCARD_LVL_DAT_DIR | Output |
SD card data direction indicates whether host is transmitting or receiving over the data.
|
88 | SDCARD_LVL_SEL | Output |
SD card level select performs the 1.8V to 3.0V negotiation.
|
91 | SDCARD_PWR_DOWN_N | Output |
SD card power down indicates to SDIO device to power down.
|
53 | SPI_1_CLK | Output |
SPI port 1 clock
|
63 | SPI_1_MISO | Input |
SPI port 1 receive data
|
55 | SPI_1_FS0 | Output |
SPI port 1 slave select 0
|
14 | SPI_1_FS2 | Output |
SPI port 1 slave select 2. Hardware strap with disable boot from SD card functionality.
|
51 | SPI_1_MOSI | Output |
SPI port 1 transmit data
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93 | UART_0_TXD | Output | UART port 0 transmit data. Hardware strap with reserved functionality. Note: Goes with UART0 signals on other connector |
26 | UART_1_RXD | Input |
UART port 1 receive data
|
28 | UART_1_TXD | Output |
UART port 1 transmit data. Hardware strap with disable boot from eMMC functionality.
|
20 | USB2_ID_PMIC | Input |
USB OTG ID for device attach/detach and USB ACA detection via detection of resistance connected to pin. Connected to PMIC USBID pin.
|
8 | USB2_0_DN | Input/Output |
USB 2.0 port 0 data negative. Connected to PMIC USB 2.0 port 0.
|
6 | USB2_0_DP | Input/Output |
USB 2.0 port 0 data positive. Connected to PMIC USB 2.0 port 0.
|
59 | USB_TYPC_CC1 | Input/Output |
USB type-C configuration channel 1. Connected to PMIC CC channel 1 pin.
|
61 | USB_TYPC_CC2 | Input/Output |
USB type-C configuration channel 2. Connected to PMIC CC channel 2 pin.
|
11 | +VRTC | Input |
Real-time clock backup battery input to PMIC.
|
92 | VBATT_SENSE | Input |
Senses when battery is plugged in
|
99 | VBUS_SENSE | Input |
Connected to +VBUS from USB for PMIC detection when USB power source is plugged in.
|
97 | VCONN_DCDC_EN | Output |
General purpose input/output controlled by PMIC to enable load switch on expansion board to supply power to USB3.0 CC pins.
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37 | VDCIN_SENSE | Input |
Connected to +VDC_IN from DC jack for PMIC detection when DC jack is plugged in.
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2, 5, 7, 12, 15, 17 | +VSYS | Input |
System power
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Note: Software enabling the Integrated Sensor Hub (ISH) is not currently available, thus the ISH_I2C_0 and ISH_I2C_1 ports are not functional. Until the ISH is enabled, the ISH_I2C_0 and ISH_I2C_1 ports have been remapped to I2C ports I2C_5 and I2C_6, respectively.
Software enabling the Integrated Sensor Hub (ISH) is not currently available, thus the ISH_GPIO_0 through ISH_GPIO_6 are not functional. Until the ISH is enabled, the ISH_GPIO_0 through ISH_GPIO_6 have been remapped to GPIO ports GPIO_146 through GPIO_153, respectively.
J7 connector interface signals
Pin | Signal Name | Usage | Description |
52 | AVS_M_CLK_A1 | Output | Microphone clock for channel A (voice trigger microphone) |
62 | AVS_M_CLK_B1 | Output | Microphone clock for channel B (secondary microphone) |
66 | AVS_M_DATA_1 | Input | First microphone pair data |
75 | FLASH_TORCH | Output | Output from shutter switch when it’s pressed full way. This switch state is used to trigger Xenon flash or LED flash |
73 | FLASH_RST_N | Input | Output from shutter switch when it’s pressed halfway. This switch state is used to trigger the Auto focus LED for Xenon Flash or Torch mode for LED flash, active low |
71 | FLASH_TRIGGER | Input | Control signal to Xenon Flash to start charging capacitor |
2, 5, 8, 10, 16, 17, 23, 24, 29, 30, 35, 36, 41, 42, 54, 60, 61, 67, 74, 80, 84, 85, 91, 90, 93, 96, 99 | GND | Ground | System ground |
43 | I2C_1_SCL | Output | I2C port 1 clock |
45 | I2C_1_SDA | Input/Output | I2C port 1 data |
9 | ISH_UART_0_CTS see Note | Input/Output |
Remapped by BIOS as GPIO_53, a general purpose input/output
|
11 | ISH_UART_0_RTS see Note | Input/Output | Remapped by BIOS as GPIO_52, a general purpose input/output |
13 | ISH_UART_0_RXD see Note | Input/Output |
Remapped by BIOS as GPIO_50, a general purpose input/output
|
15 | ISH_UART_0_TXD see Note | Input/Output |
Remapped by BIOS as GPIO_51, a general purpose input/output
|
26 | I2C_2_SDA | Input/Output | I2C port 2 data |
28 | I2C_2_SCL | Output | I2C port 2 clock |
12, 14, 38, 40, 69, 81, 83, 92, 94, 98, 100 | Reserved | Reserved | Do not use; leave disconnected |
88 | PCIE1_CLK_DN | Output | PCIe port 1 clock negative |
86 | PCIE1_CLK_DP | Output | PCIe port 1 clock positive |
50 | PCIE1_CLKREQ_N | Input | PCIe port 1 clock request, active low |
72 | PCIE1_WAKE_N | Input | PCIe wake, active low |
70 | PCIE1_PERST_N | Output | PCIe reset, active low |
95 | PCIE_RX_DP | Input | PCIe receive data positive |
97 | PCIE_RX_DN | Input | PCIe receive data negative |
87 | PCIE_TX_DP | Output | PCIe transmit data positive |
89 | PCIE_TX_DN | Output | PCIe transmit data negative |
7
| PMIC_SLPCLK_1 | Output | 32kHz RTC |
59 | SPI_0_CLK | Output | SPI port 0 clock |
49 | SPI_0_MISO | Input | SPI port 0 receive data |
77 | SPI_0_FS0 | Output | SPI port 0 chip select 0. Hardware strap with reserved functionality. |
79 | SPI_0_FS1 | Output | SPI port 0 chip select 1. Hardware strap with reserved functionality. |
53 | SPI_0_FS2 | Output | SPI port 0 chip select 2 |
57 | SPI_0_MOSI | Output | SPI port 0 transmit data |
47 | UART_0_CTS | Input | UART port 0 clear to send |
55 | UART_0_RTS | Output | UART port 0 return to send |
51 | UART_0_RXD | Input | UART port 0 receive data (note UART_0_TXD is on the other 100p connector) |
18 | USBC_SEL | Output | PMIC mux control for USB type-C polarity |
63 | USB2_1_DN | Input/Output | USB 2.0 data negative |
65 | USB2_1_DP | Input/Output | USB 2.0 data positive |
44 | USB3_0_RX_DN | Input | USB 3.0 data receive negative |
46 | USB3_0_RX_DP | Input | USB 3.0 data receive positive |
6 | USB3_0_TX_DN | Output | USB 3.0 data transmit negative |
4 | USB3_0_TX_DP | Output | USB 3.0 data transmit positive |
95 | USB3_1_RX_DP | Input | USB 3.0 data receive negative |
97 | USB3_1_RX_DN | Input | USB 3.0 data receive positive |
89 | USB3_1_TX_DN | Output | USB 3.0 data transmit negative |
87 | USB3_1_TX_DP | Output | USB 3.0 data transmit positive |
1, 3, 20, 22, 32, 34 | VSYS | Input | System power |
Note: Software enabling the Integrated Sensor Hub (ISH) is not currently available. The ISH_UART_0 is not functional. Until the ISH is enabled, the ISH_UART_0 port has been remapped to GPIO ports.