• 07/14/2017
  • Public Content
Contents

Breakout Connectors

The expansion board contains two forty-pin connectors, each having a 2x20 configuration at 0.1-inch spacing, to enable external circuit connections.
These connectors are referred to as the breakout connectors. They expose several interfaces and module signals required to develop complete systems.
These breakout connectors provide access to the following interfaces:
  • Two SPI ports
  • Three UARTs
  • Five I2C ports
  • One I2S port
  • Four PWM interfaces
  • Eight dedicated GPIO signals, and seven user programmable GPIO signals
  • Two digital microphone inputs
  • Various voltage rails and power signals
The expansion board provides open collector type level translation (shifting) of the module 1.8 VDC I/O lines and requires pullups on the attached mezzanine cards to the end-user’s desired voltage levels typically used in the development phase, not to exceed 3.3 VDC. Details of any level translation, conditioning or buffering applied by the expansion board are found in the respective sections for those specific interfaces where such is applied.
Pinmapping for the breakout connectors can be found in Default Pinmapping for the Expansion Board. The table provides the pin assignment, signal name, and description for the signals on the breakout connectors J12 and J13. The table below depicts power-on and default BIOS only. These signals are mapped by various operating systems in different ways. For other operating system and other configurations, see Pinmapping for the Expansion Board.
 

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804