• 07/14/2017
  • Public Content
Contents

DMIC Interface

The Intel® Joule™ module supports microphones that use the PDM digital microphone standard attached through the AVS_M interface. Two microphones can share one data line by using time domain multiplexing to the two slots.
PDM microphones are enabled and disabled by the clock signal. Absence of clock signal will switch microphone to sleep mode, which can be utilized in system power management.
Additionally, the microphones can be power-gated to cut power consumption to zero when the microphones are not in use.
Refer to I2S Interface Specifications for additional information.
DMIC Signal Termination and Conditioning
For information about signal termination and conditioning, definitions of the values in the following table, and how the values were measured, refer to Termination and Conditioning. For an example of how to wire a pullup resistor for a 3.3 V pullup voltage, refer to GPIO Signal Termination and Conditioning.
DMIC signal level translation termination recommendations
Signal Name
Pullup Voltage
R
min
(Ω)
CLOAD (pF)
T
rise
(ns)
T
fall
(ns)
AVS_M_CLK_A1_LS
AVS_M_CLK_B1_LS
AVS_M_DATA_1_LS
3.3
1100
47
184
17
 

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.