• 07/14/2017
  • Public Content
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GPIOs

The expansion board provides 8 dedicated GPIO lines and 7 additional GPIO lines at the breakout connectors; the first four GPIO lines (ISH_GPIO_0 through ISH_GPIO_3) are also connected to onboard LEDS that are activated when the line is HIGH from either the breakout source or the module. See General Purpose LEDs in Buttons Jumpers and LEDs for the mapping of GPIO to LEDs.
All 15 GPIOs are level shifted by a by a Texas Instruments* LSF0108RKSR device and require pullups on the attached mezzanine cards to the end-user’s desired voltage levels not to exceed 3.3 VDC. Level transition circuits for GPIO lines must be powered and stable before the module completes the cold boot routine.
The default pin usage refers to the vantage point of the breakout board. For example, the ISH_GPIO_0 signal originates in the breakout board and is delivered to the expansion board through the J12 connector; therefore ISH_GPIO_0 is an output (as configured by the BIOS).
GPIO Mapping Table
Pin #
Signal Name
Default Breakout Usage
Signal Description
J12.1
GPIO_22
Input
GPIO Pin 14
J12.35
ISH_GPIO_0_LS
Output
GPIO Pin 0
J12.33
ISH_GPIO_1_LS
Output
GPIO Pin 1
J12.31
ISH_GPIO_2_LS
Output
GPIO Pin 2
J12.29
ISH_GPIO_3_LS
Output
GPIO Pin 3
J12.27
ISH_GPIO_4_LS
Output
GPIO Pin 4
J12.25
ISH_GPIO_5_LS
Output
GPIO Pin 5
J12.23
ISH_GPIO_6_LS
Output
GPIO Pin 6
J13.16
FLASH_TORCH
Output
GPIO Pin 7
J13.18
FLASH_RST_N
Output
GPIO Pin 8
J13.20
FLASH_TRIGGER
Output
GPIO Pin 9
J13.34
ISH_UART_0_TXD
Output
GPIO Pin 10
J13.36
ISH_UART_0_RXD
Output
GPIO Pin 11
J13.38
ISH_UART_0_RTS
Output
GPIO Pin 12
J13.40
ISH_UART_0_CTS
Input
GPIO Pin 13
Note: 
 During BIOS execution, the ISH_GPIO_0 through ISH_GPIO_3 signals are configured as outputs and change state to indicate BIOS progression.

Product and Performance Information

1

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Notice revision #20110804