• 07/14/2017
  • Public Content
Contents

Control Signal Termination and Conditioning

Additional buffering is needed for the PMIC_RESET_N_LS signal because the typical level translation does not use a strong enough pullup to 3.3 volts. The nFET transistor pairs have low Vts (part number DMN2400) operating at 1.5 V or 1.8 V levels, and offer the high-impedance level shifting requirement for this signal.
Signal Name
Pullup Voltage
R
min
(Ω)
CLOAD (pF)
T
rise
(ns)
T
fall
(ns)
PMIC_PWRGOOD_LS
3.3
2200
47
36800
19
PMIC_RESET_N_LS
Add a non-inverting buffer to the PMIC_RESET_LS signal
 
 
Refer to
Termination and Conditioning for a discussion of signal termination, how the values in the table were measured, and definitions of the values in the table. Refer to
for an example pullup resistor for 3.3 V pullup voltage.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.