• 07/14/2017
  • Public Content
Contents

Signal Conditioning and Routing

Display Data Channel (DDC)
The compute module DDC lines are open-drain 1.8 V signals.
Board designers must level-shift the DDC signals to 1.8 V levels before they reach the module. Level-shifting can be accomplished using several methods including discrete circuitry or with an active level shifting device. The reference expansion board performs the level-shifting of the DDC signals with an HDMI re-driver device.
Note
: The HDMI source side DDC signals on some HDMI re-driver solutions may operate at 3.3 V. Be aware that if one of these devices is selected, the DDC signals will require additional level-shifting to 1.8 V levels.
Hot-Plug Detect (HPD)
The compute module hot-plug detect (HPD) is an active-low 1.8 V signal.
Board designers must invert the logic of, and level-shift the HPD signal to 1.8 V levels before it reaches the module. Level-shifting can be accomplished using several methods including discrete circuitry or with active level-shifting and signal inversion devices. The reference expansion board performs the level-shifting of the HPD signal with an HDMI re-driver device and uses an N-FET to complete the logic inversion.
Note: The HDMI source side HPD signal on some HDMI re-driver solutions may operate at 3.3 V. Be aware that if one of these devices is selected, the HPD signal will require additional level-shifting to 1.8 V levels.
Additional Recommendations
  • Add series capacitors near the module connector on the HDMI clock and data lines.
  • Include common-mode chokes with built-in ESD protection on the HDMI clock and data lines between the HDMI connector and the re-driver or termination circuitry.
  • Follow general high-speed layout guidelines when routing HDMI clock and data lines. See Differential Trace Information for module specific routing information.
  • Add ESD protection diodes to the HPD and DDC signals near the HDMI connector if not provided by a re-driver component.
  • The DDC and 5 V lines from the the HDMI connector should be isolated from the board's 5 V rail with backdrive prevention diodes.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804