• 07/14/2017
  • Public Content
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Required Straps

The boot behavior of the SoC on the module can be influenced by a number of strap signals. The table below shows the configuration of the straps for normal operation. It is the designer’s responsibility to ensure that their design does not impact the default signal levels; that is, the signals must remain in the default states until the PMIC_RESET is de-asserted.
 
Signal Name
Connector.Pin
Default
Requirement
UART_0_TXD
J6.93
Internal 20k pull down
Must be Hi-Z or pulled down to GND each time PMIC_PWRGOOD asserts
ISH_UART_0_RTS
J7.11
Internal 20k pull up
Must be Hi-Z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts
ISH_UART_0_TXD
J7.15
Internal 20k pull down
Must be Hi-Z or pulled down to GND each time PMIC_PWRGOOD asserts
SPI_0_FS0
J7.77
Internal 20k pull up
Must be Hi-Z or pulled down to GND each time PMIC_PWRGOOD asserts
SPI_0_FS1
J7.79
Internal 20k pull up
Must be Hi-Z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts
SPI_1_FS2
J6.14
Internal 20k pull up
Must be Hi-Z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts
 
See Module Sideband and GPIO Control Signals for more information about the PMIC_PWRGOOD signal.

Product and Performance Information

1

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Notice revision #20110804