• 07/14/2017
  • Public Content
Contents

UART Interfaces

The Intel® Joule™ module provides two serial UARTs for user modification: UART0 and UART_1.
Refer to UART Interface Specifications for additional electrical specifications.
Debug Console Port
UART2 is configured in BIOS as the debug UART, allowing BIOS output and console access from the Linux* operating system.
The figure below shows a typical design with a USB-to-UART bridge and a level shifter for translating the 1.8 V module signals to the 3.3 V levels required by the bridge.
The USB-to-UART bridge is powered either from a 5 V supply (see figure in Platform Power Supply (Simplistic Model)), or from the USB device connector; the simplest method for this is a dual source, each with a protection diode.
 
Note
: The debug UART uses four pins on J6; these can be routed to a debug connector of choice.
 
Signal
Module Connector.Pin
Pin Direction
Use
DEBUG_UART2_TXD
J6.78
Input
UART 2 TXD – configured in BIOS as debug output port
DEBUG_UART2_RXD
J6.80
Output
UART 2 RXD – configured in BIOS as debug output port
DEBUG_UART2_CTS
J6.74
Output
UART 2 CTS – configured in BIOS as debug output port
DEBUG_UART2_RTS
J6.76
Input
UART 2 RTS – configured in BIOS as debug output port
UART to USB Bridge Power
When the module is powered off, it must be isolated from a powered USB-to-UART bridge to prevent current leaking through the UART lines. This can be done by disabling the level shifter through the +VDD1 rail.
To satisfy the pin strap requirements in Required Straps, the level shifter needs to be directional to prevent the bridge from pulling the TX line high.
If a 1.8 V-compatible USB-to-UART bridge is used, the level shifter can be replaced with a switch enabled by the +VDD1 rail.
The USB differential data lines need a common-mode choke with built-in ESD diodes.
For +VBUS, add ESD protection diodes, a PTC fuse, and a ferrite for EMI filtering.

Product and Performance Information

1

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Notice revision #20110804