• 07/14/2017
  • Public Content


Feature Overview
The Display interface and Blitter (block image transferrer) are controlled primarily by direct CPU register addresses, while the 3D and Media pipelines and the parallel Video Codec Engine (VCE) are controlled primarily through instruction lists in memory.
The Intel Gen9 Display Engine offers impressive graphics capabilities and supports:
  • 3-D rendering
  • media composting
  • video decoding / encoding methods:
    • AVC (H.264)
    • HEVC (H.265)
    • VP8 and VP9
  • DirectX* (9.3, 10, 11.3, 12)
  • OpenGL# 4.3 and OGL ES 3.1
  • OpenCL* 2.0
  • 4x anti-aliasing
  • content protection using PAVP 2.0
Media Framework
The media framework of the Ref-OS-IoT provides audio/video playback, record, streaming, image capture and metadata gathering support.
The framework is built with a combination of GStreamer, ALSA, software & hardware accelerated Codecs, Intel® Imaging stack and Linux* connectivity frameworks such as ConnMan and bluez.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804