• 2019 Update 4
  • 03/20/2019
  • Public Content
Contents

Avoiding Needless Synchronization

For best results, try to avoid explicit command synchronization primitives (such as
clEnqueueMarker
or
Barrier),
also explicit synchronization commands and event tracking result in cross-module round trips, which decrease performance. The less you use explicit synchronization commands, the better the performance.
Use the following techniques to reduce explicit synchronization:
  • Continue executing kernels until you really need to read the results; this idiom best expressed with in-order queue and blocking call to
    clEnqueueMapXXX
    or
    clEnqueueReadXXX
    .
  • If an in-order queue expresses the dependency chain correctly, exploit the in-order queue rather than defining an event-driven string of dependent kernels. In the in-order execution model, the commands in a queue are automatically executed back-to-back, in the order of submission. This suits very well a typical case of a processing pipeline. Consider the following recommendations:
    • Avoid any host intervention to the in-order queue (like blocking calls) and additional synchronization costs.
    • When you have to use the blocking API, use OpenCL™ API, which is more effective than explicit synchronization schemes, based on OS synchronization primitives.
    • If you are optimizing the kernel pipeline, first measure kernels separately to find the most time-consuming one. Avoid calling
      clFinish
      or
      clWaitForEvents
      frequently (for example, after each kernel invocation) in the final pipeline version. Submit the whole sequence (to the in-order queue) and issue
      clFinish
      (or wait on the event) once. This reduces host-device round trips.
    • Consider OpenCL 2.0 “enqueue_kernel” feature that allows a kernel to independently enqueue to the same device, without host interaction. Notice that this approach is useful not just for recursive kernels, but also for regular non-recursive chains of the lightweight kernels. Refer to the
      See Also
      section below.
See Also

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804