• 2019 Update 4
  • 03/20/2019
  • Public Content
Contents

Aligning Pointers to Microsoft DirectX* Buffers Upon Mapping

If your application utilizes resource sharing with Microsoft DirectX* 10 or 11 by use of mapping, use the
CL_MEM_USE_HOST_PTR
flag. Also note that mapping is less efficient than using the
cl_khr_d3d10_sharing
or
cl_khr_d3d11_sharing
.
Consider the general interoperability flow:
  1. Map a resource to CPU
  2. Create a buffer wrapping the memory
  3. Use the buffer by use of the OpenCL™ regular commands
  4. Upon competition of the OpenCL commands, the resource can be safely unmapped.
Now use the
CL_MEM_USE_HOST_PTR
flag to directly operate on the mapped memory and avoid data copying upon OpenCL buffer creation. This method requires properly aligned memory. See the “Mapping Memory Objects” section for more information.
Note
Aligning might result in unprocessed data between original and aligned pointer.
If it is acceptable for your application, and/or the copying overhead is of concern, consider aligning of the pointer returned by the DirectX map call to comply with the "Mapping Memory Objects" section.
Another potential workaround is to allocate larger DirectX resource than it is required, so that you have some room for a safe alignment. This approach requires some additional application logic.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804