OpenCL™ Developer Guide for Intel® Processor Graphics
2019 Update 4
Kernel Memory Access Optimization Summary
A kernel should access at least 32-bits of data at a time, from addresses that are aligned to 32-bit boundaries. A
-bits of data. If you can, load two, three, or four
-bit quantities at a time, which may improve performance. Loading more than four
-bit quantities at a time may reduce performance.
memory accesses to minimize the number of cache lines read from the L3 cache. This typically involves carefully choosing your work-group dimensions, and how your array indices are computed from the work-item local or global id.
If you cannot access
memory in an optimal manner, consider moving part of your data to
memory, where more access patterns can execute with full performance.
Local memory is most beneficial when the access pattern favors the banked nature of the SLM hardware.
memory accesses to minimize the number of bank conflicts. Reading the same address from the same bank is OK, but reading different addresses from the same bank results in a bank conflict. Writes to the same bank always result in a bank conflict, even if the writes are going to the same address. Consider adding a column to two-dimensional local memory arrays if it avoids bank conflicts when accessing columns of data.