• 2019 Update 4
  • 03/20/2019
  • Public Content
Contents

Synchronization Caveats

Similarly to the regular case of multiple queues within the same context, you can wait on event objects from CPU and GPU queue (error checking is omitted):
cl_event eventObjects[2]; //notice that kernel object itself can be the same (shared) clEnqueueNDRangeKernel(gpu_queue, kernel, … &eventObjects[0]); //other commands for the GPU queue //… //flushing queue to start execution on the Intel® Graphics in parallel to populating to the CPU queue below //notice it is NOT clFinish or clWaitForEvents to avoid serialization clFlush(gpu_queue);//assuming NO RESOURCE or other DEPENDENCIES with CPU device clEnqueueNDRangeKernel(cpu_queue, kernel, … &eventObjects[1]); //other commands for the CPU queue //… //now let’s flush second queue clFlush(cpu_queue); //now when both queues are flushed, let’s wait for both kernels to complete clWaitForEvents(2, eventObjects);
In this example the first queue is flushed without blocking and waiting for results. In case of blocking calls like
clWaitForEvents
and
clFinish
, the actions are serialized with respect to devices. The reason is that in this example the commands do not get into the (second) queue before
clWaitForEvents and
clFinish
in the first queue return (assuming you are in the same thread).
For the example, when proper serialization is critical refer to the "Writing to a Shared Resource" section.
See Also

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804