• 10/30/2018
  • Public Content
Contents

About This Document

This guide describes the optimization guidelines of OpenCL™ applications targeting the Intel® Core™ and Intel® Xeon® Processors.
In case your application targets Intel® processors with Intel® Graphics, refer to the corresponding
OpenCL™ Developer Guide for Intel® Processor Graphics.
Note
Intel® Xeon Phi™ coprocessor based on the Intel® Many Integrated Core (Intel® MIC) Architecture is supported only on OpenCL™ Runtime version 14.2.
This guide describes three basic factors most influence performance on the multi-socket systems:
  • Threading scalability
    . Multi-socket Intel Xeon systems combine many Intel® CPU cores, thus utilizing thread parallelism is critical to achieving good performance.
  • Vectorization
    . Intel Xeon processors support wide vector registers and associated SIMD operations.
  • Memory bandwidth utilization
    .
This guide explains, which sections of code consume most compute cycles, and provides optimization best-known methods.
For better understanding of the optimizations described in this guide, you must be familiar with the following concepts:
  • The OpenCL standard
  • Threading and Single Instruction Multiple Data (SIMD) vector instruction sets

See Also

OpenCL™ 1.2 Specification at
Overview Presentations of the OpenCL™ Standard at

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804