Developer Guide

Dispatching

Intel® IPP Cryptography uses multiple function implementations optimized for various CPUs. Dispatching refers to detection of your CPU and selecting the corresponding Intel IPP Cryptography binary path.
For example, the
ippcp
library in the
/redist/intel64/ippcp
directory contains cryptographic functions optimized for 64-bit applications on processors with Intel® Advanced Vector Extensions (Intel® AVX) enabled such as the 2
nd
Generation Intel® Core™ processor family.
A single Intel IPP Cryptography function, for example
ippsSHA256Update()
, may have many versions, each one optimized to run on a specific Intel® processor with specific architecture, for example, the 64-bit version of this function optimized for the 2
nd
Generation Intel® Core™ processor is
e9_ippsSHA256Update()
, and the version optimized for 64-bit applications on processors with Intel® Streaming SIMD Extensions 4.2 (Intel® SSE 4.2) is
y8_ippsSHA256Update()
. This means that a prefix before the function name determines the CPU model. However, during normal operation the dispatcher determines the best version and you can call a generic function (
ippsSHA256Update()
in this example).
Intel® IPP Cryptography is designed to support application development on various Intel® architectures. This means that the API definition is common for all processors, while the underlying function implementation takes into account the strengths of each hardware generation.
By providing a single cross-architecture API, Intel IPP Cryptography enables you to port features across Intel® processor-based desktop, server, and mobile platforms. You can use your code developed for one processor architecture for many processor generations.
The following table shows processor-specific codes that Intel IPP Cryptography uses:
Description of Codes Associated with Processor-Specific Libraries
 IA-32 Intel® architecture
 Intel® 64 architecture
Windows*
Linux* OS
Android*
macOS*
Description
w7
+
+
Optimized for processors with Intel SSE2
s8
n8
+
+
+
Optimized for processors with Supplemental Streaming SIMD Extensions 3 (SSSE3)
m7
+
+
+
+
Optimized for processors with Intel SSE3
p8
y8
+
+
+
+
Optimized for processors with Intel SSE4.2
g9
e9
+
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions (Intel® AVX) and Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
h9
l9
+
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions 2 (Intel® AVX2)
k0
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
n0
+
+
Optimized for processors with Intel® Advanced Vector Extensions 512 (Intel(R) AVX-512) for Intel(R) Many Integrated Core Architecture (Intel(R) MIC Architecture)
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.
Notice revision #20201201

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.