Developer Reference

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SHA1MessageDigest

Computes SHA-1 digest value of the input message.

Syntax

IppStatus ippsSHA1MessageDigest(const Ipp8u *
pMsg
, int
len
, Ipp8u *
pMD
);
Include Files
ippcp.h
Parameters
pMsg
Pointer to the input message.
len
Message length in octets.
pMD
Pointer to the resultant digest.
Description
The function uses the selected hash algorithm to compute the digest value of the entire (non-streaming) input message.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or warning.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsLengthErr
Indicates an error condition if the input data stream length is less than zero.

Example

The code example below shows SHA1 digest of a message.
// Compute two SHA1 digests of a message: // 1-st will correspond of 1/2 message // 2-nd will correspond of whole message void SHA1_sample(void){ // get size of the SHA1 context int ctxSize; ippsSHA1GetSize(&ctxSize); // allocate the SHA1 context IppsSHA1State* pCtx = (IppsSHA1State*)( new Ipp8u [ctxSize] ); // and initialize the context ippsSHA1Init(pCtx); // define a message Ipp8u msg[] = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; int n; // update digest using a piece of message for(n=0; n<(sizeof(msg)-1)/2; n++) ippsSHA1Update(msg+n, 1, pCtx); // clone the SHA1 context IppsSHA1State* pCtx2 = (IppsSHA1State*)( new Ipp8u [ctxSize] ); ippsSHA1Init(pCtx2); ippsSHA1Duplicate(pCtx, pCtx2); // finalize and extract digest of a half message Ipp8u digest[20]; ippsSHA1Final(digest, pCtx); // update digest using the SHA1 clone context ippsSHA1Update(msg+n, sizeof(msg)-1-n, pCtx2); // finalize and extract digest of a whole message Ipp8u digest2[20]; ippsSHA1Final(digest2, pCtx2); delete [] (Ipp8u*)pCtx; delete [] (Ipp8u*)pCtx2; }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804