Developer Reference

Contents

DLPGenerateDH

Generates domain parameters of the DL-based cryptosystem over GF(p) to use the DH Agreement scheme.

Syntax

IppStatus ippsDLPGenerateDH(const IppsBigNumState*
pSeedIn
, int
nTrials
, IppsDLPState*
pCtx
, IppsBigNumState*
pSeedOut
, int*
pCounter
, IppBitSupplier
rndFunc
, void*
pRndParam
);
Include Files
ippcp.h
Parameters
pSeedIn
Pointer to the input
Seed
.
nTrials
Security parameter specified for the Miller-Rabin probable primality.
pCtx
Pointer to the cryptosystem context.
pSeedOut
Pointer to the output
Seed
value (if requested).
pCounter
Pointer to the
counter
value (if requested).
rndFunc
Specified Random Generator.
pRndParam
Pointer to the Random Generator context.
Description
The function generates domain parameters of the DL-based cryptosystem over GF(
p
) to use Diffie-Hellman Agreement scheme. The function uses a procedure specified in [X9.42] for generating both randomized prime
p
and
r
based on the input
*pSeedIn
.
Generated primes
r
and
p
are further validated through a
nTrial
-round Miller-Rabin primality test. Both generation and primality test procedures employ specified
rndFunc
Random Generator.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or warning.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsContextMatchErr
Indicates an error condition if the context parameter does not match the operation.
ippStsSizeErr
Indicates an error condition if:
peBits
< 512 or
reBits
< 160,
peBits
is not divided by 256.
ippStsRangeErr
Indicates an error condition if: bitsize of the input
Seed
value is less than
reBits
, not enough space to store the output
Seed
value (if requested).
ippStsBadArgErr
Indicates an error condition if
nTrials
< 1.
ippStsInsuffucientEntropy
Indicates a warning condition if prime generation fails due to a poor choice of the entropy.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804