Developer Reference

Contents

DLPSignDSA

Performs the DSA digital signature signing operation.

Syntax

IppStatus ippsDLPSignDSA(const IppsBigNumState*
pMsg
, const IppsBigNumState*
pPrivate
, IppsBigNumState*
pSignR
, IppsBigNumState*
pSignS
, IppsDLPState*
pCtx
);
Include Files
ippcp.h
Parameters
pMsg
Pointer to the message representation
msgRep
to be signed.
pPrivate
Pointer to the signer's private key
privKey
.
pSignR
Pointer to the
r
-component of the signature.
pSignS
Pointer to the
s
-component of the signature.
pCtx
Pointer to the cryptosystem context.
Description
The function performs the DSA digital signature signing operation provided that the ephemeral signer's key pair (both private and public) was previously computed (generated by
DLPGenKeyPair
or computed by
DLPPublicKey
) and then set up into the DLP context by the
DLPSetKeyPair
function.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or warning.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsContextMatchErr
Indicates an error condition if the context parameter does not match the operation.
ippStsIncompleteContextErr
Indicates an error condition if the cryptosystem context has not been properly set up.
ippStsMessageErr
Indicates an error condition if the value of
msgRep
is greater than the multiplicative subgroup characteristic (
q
).
ippStsInvalidPrivateKey
Indicates an error condition if an illegal value has been assigned to
privKey
.
ippStsRangeErr
Indicates an error condition if any of the signature components has not enough space.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804