Developer Reference

Contents

DLPValidateDSA

Validates domain parameters of the DL-based cryptosystem over GF(p) to use DSA.

Syntax

IppStatus ippsDLPValidateDSA(int
nTrials
, IppDLResult*
pResult
, IppsDLPState*
pCtx
, IppBitSupplier
rndFunc
, void*
pRndParam
);
Include Files
ippcp.h
Parameters
nTrials
Security parameter specified for the Miller-Rabin probable primality.
pResult
Pointer to the validation result.
pCtx
Pointer to the cryptosystem context.
rndFunc
Specified Random Generator.
pRndParam
Pointer to the Random Generator context.
Description
The function validates domain parameters of the DL-based cryptosystem over GF(
p
) to use DSA. The result of validation is stored in the
*pResult
and may be assigned to one of the enumerators listed below:
ippDLValid
Validation has passed successfully.
ippDLBaseIsEven
P
is even.
ippDLOrderIsEven
R
is even.
ippDLInvalidBaseRange
P
2
peBits-1
or
P
2
peBits
.
ippDLInvalidOrderRange
R
2
reBits-1
or
R
2
reBits
.
ippDLCompositeBase
P
is not a prime.
ippDLCompositeOrder
R
is not a prime.
ippDLInvalidCofactor
R
is not divisible by (
P
-1).
ippDLInvalidGenerator
(1 <
G
< (
P
-1)) is false or
G
^
R
!= 1 (mod
P
).
To ensure that both
p
and
r
are primes, the function applies
nTrial
-round Miller-Rabin primality test. Test data for primality test is provided by the specified
rndFunc
Random Generator.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or warning.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsContextMatchErr
Indicates an error condition if the context parameter does not match the operation.
ippStsIncompleteContextErr
Indicates an error condition if the cryptosystem context has not been properly set up.
ippStsBadArgErr
Indicates an error condition if
nTrials
< 1.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804