Developer Reference

  • 8.1
  • 07/15/2020
  • Public Content
Contents

GetCpuFeatures

Retrieves the processor features.

Syntax

IppStatus ippсpGetCpuFeatures(Ipp64u*
pFeaturesMask
);
Include Files
ippcp.h
Parameters
pFeaturesMask
Pointer to the features mask. Possible value is
ippCPUID_GETINFO_A
.
Description
This function retrieves some of the CPU features returned by the function CPUID.1 and stores them consecutively in the mask
pFeaturesMask
. The following table lists the features stored in the mask.
Mask Value
Bit Name
Feature
Mask Bit Number
0x00000001
ippCPUID_MMX
MMX™ technology
0
0x00000002
ippCPUID_SSE
Intel® Streaming SIMD Extensions
1
0x00000004
ippCPUID_SSE2
Intel® Streaming SIMD Extensions 2
2
0x00000008
ippCPUID_SSE3
Intel® Streaming SIMD Extensions 3
3
0x00000010
ippCPUID_SSSE3
Supplemental Streaming SIMD Extensions
4
0x00000020
ippCPUID_MOVBE
MOVBE instruction is supported
5
0x00000040
ippCPUID_SSE41
Intel® Streaming SIMD Extensions 4.1
6
0x00000080
ippCPUID_SSE42
Intel® Streaming SIMD Extensions 4.2
7
0x00000100
ippCPUID_AVX
The processor supports Intel® Advanced Vector Extensions (Intel® AVX) instruction set
8
0x00000200
ippAVX_ENABLEDBYOS
The operating system supports Intel® AVX
9
0x00000400
ippCPUID_AES
Advanced Encryption Standard (AES) instructions are supported
10
0x00000800
ippCPUID_CLMUL
PCLMULQDQ instruction is supported
11
0x00002000
ippCPUID_RDRAND
Read Random Number instructions are supported
13
0x00004000
ippCPUID_F16C
16-bit floating point conversion instructions are supported
14
0x00008000
ippCPUID_AVX2
Intel® Advanced Vector Extensions 2 (Intel® AVX2) instruction set is supported
15
0x00010000
ippCPUID_ADCOX
ADCX and ADOX instructions are supported
16
0x00020000
ippCPUID_RDSEED
Read Random SEED instruction is supported.
17
0x00040000
ippCPUID_PREFETCHW
PREFETCHW instruction is supported
18
0x00080000
ippCPUID_SHA
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) are supported
19
0x00100000
ippCPUID_AVX512F
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) foundation instructions are supported
20
0x00200000
ippCPUID_AVX512CD
Intel® AVX-512 conflict detection instructions are supported
21
0x00400000
ippCPUID_AVX512ER
Intel® AVX-512 exponential and reciprocal instructions are supported
22
0x80000000
ippCPUID_KNC
Intel® Xeon Phi™ is supported
23
Intel
®
Itanium
®
processors are not supported.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error condition when the
pFeaturesMask
pointer is
NULL
.
ippStsNotSupportedCpu
Indicates that the processor is not supported.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804