Developer Guide

Contents

Dispatching

Intel® IPP uses multiple function implementations optimized for various CPUs. Dispatching refers to detection of your CPU and selecting the corresponding Intel IPP binary path.
For example, the
ippie9
library in the
/redist/intel64/ipp
directory contains the image processing libraries optimized for 64-bit applications on processors with Intel® Advanced Vector Extensions (Intel® AVX) enabled such as the 2
nd
Generation Intel® Core™ processor family.
A single Intel IPP function, for example
ippsCopy_8u()
, may have many versions, each one optimized to run on a specific Intel® processor with specific architecture, for example, the 64-bit version of this function optimized for the 2
nd
Generation Intel® Core™ processor is
e9_ippsCopy_8u()
, and version optimized for 64-bit applications on processors with Intel® Streaming SIMD Extensions 4.2 (Intel® SSE 4.2) is
y8_ippsCopy_8u()
. This means that a prefix before the function name determines CPU model. However, during normal operation the dispatcher determines the best version and you can call a generic function (
ippsCopy_8u
in this example).
Intel® IPP is designed to support application development on various Intel® architectures. This means that the API definition is common for all processors, while the underlying function implementation takes into account the strengths of each hardware generation.
By providing a single cross-architecture API, Intel IPP enables you to port features across Intel® processor-based desktop, server, and mobile platforms. You can use your code developed for one processor architecture for many processor generations.
The following table shows processor-specific codes that Intel IPP uses:
Description of Codes Associated with Processor-Specific Libraries
 IA-32 Intel® architecture
 Intel® 64 architecture
Windows*
Linux* OS
macOS*
Description
w7
+
+
Optimized for processors with Intel SSE2
m7
+
+
Optimized for processors with Intel SSE3
s8
n8
+
+
Optimized for processors with Supplemental Streaming SIMD Extensions 3 (SSSE3)
p8
y8
+
+
+
Optimized for processors with Intel SSE4.2
g9
e9
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions (Intel® AVX) and Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
h9
l9
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions 2 (Intel® AVX2)
n0
+
+
Optimized for 2nd Generation Intel® Xeon Phi™ Processor
k0
+
+
+
Optimized for processors with Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804