Developer Guide

Contents

Managing Memory Allocations

In Intel Integrated Performance Primitives (Intel® IPP) functions, the areas in memory allocated for the source and destination data must not overlap, except for functions that have the descriptor
I
in their name. Only the functions that have the descriptor
I
(see Descriptors) in their name can have the same area in memory allocated for both the source and destination data. Intel IPP does not guarantee correct behavior and results for not-in-place functions that are used in in-place mode.
Depending on the implementation layer and the specific operation parameters, some Intel IPP functions need varying amounts of memory for internal structures and working buffers. To address this, follow the steps below:
  1. Compute the size of the required buffer using the
    <function base name>
    GetSize
    function (some functions have
    GetBufSize
    or
    GetBufferSize
    in their name instead of
    GetSize
    ).
  2. Set up any buffers needed for initialization. For more information, see the section Setting up Buffers below.
  3. Initialize the specification or state structure for the operation using
    <function base name>
    Init
    function. For more information about the specification and state structures, see the section Specification and State Structures below.
  4. Free the buffers need for initialization only (the ones you set up in step 2).
  5. Set up working buffers for the main operation. For more information, see the section Setting up Buffers below.
  6. Do the main operation.
  7. Free the specification or state buffers that you set up in step 3 and the working buffers that you set up in step 5.
If you use several Intel IPP functions with the
pBuffer
parameter (external memory buffer), for better efficiency and performance it is recommended to call all
<function base name>
GetSize
functions in one single location within your application and allocate only one buffer that has the largest size. This approach ensures optimal use of system memory and all cache levels.

Setting up Buffers

In this document, "setting up a buffer" refers to allocating the required amount of memory and providing a pointer to this memory to the Intel IPP function you are calling. For better performance, you should allocate aligned memory buffers, where the alignment factor depends on the architecture and should be at least 16 bytes for Intel® Streaming SIMD Extensions, 32 bytes for Intel® Advanced Vector Extensions, and 64 bytes for Intel® Advanced Vector Extensions 512 Foundation instruction sets.
To set up aligned memory buffers, it is recommended to use the
ipp
<domain letter>
Malloc_
<IPP data type>
functions; these functions always provide memory buffers with the required alignment.
Intel IPP functions do not allocate any memory internally. You must manually allocate any memory your Intel IPP functions require at the application level.
ipp
<domain letter>
Malloc_
<IPP data type>
functions do not use any memory manager specific to Intel IPP and are just wrappers for the current C runtime
malloc()
function.

Specification and State Structures

Specification, or spec, structures are
const
; an instance of a specification structure does not change between Intel IPP function calls. Therefore, you can use one instance of a specification structure simultaneously in different application threads for the same operation.
State structures are not
const
; they always contain the state of an intermediate computation stage of an Intel IPP function. Therefore, you can use a single instance of a state structure only for consecutive operations. In the case of a threaded application, each thread must have its own instance of the state structure.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804