Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DecodeBlock_BZ2

Performs the bzip2-specific block decoding.

Syntax

IppStatus ippsDecodeBlock_BZ2_16u8u(const Ipp16u*
pSrc
, int
srcLen
, Ipp8u*
pDst
, int*
pDstLen
, int
index
, int
dictSize
, const Ipp8u
inUse
[256], Ipp8u*
pBuff
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source vector.
srcLen
Pointer to the length of the source vector.
pDst
Pointer to the destination vector.
pDstLen
Pointer to the size of destination buffer on input, pointer to the resulting length of the destination vector on output.
index
Index of first position for the inverse BWT transform
dictSize
Size of the reduced dictionary.
inUse
Table of 256 values of
Ipp8u
type.
pBuff
Pointer to the additional buffer.
Description
This function performs the bzip2-specific block decoding. The function uses the bzip2-specific additional buffer
pBuff
. The size of this buffer must be computed by the function DecodeBlockGetSize_BZ2 beforehand.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the pointers is
NULL
.
ippStsSizeErr
Indicates an error if length of the source or destination buffer is less than or equal to 0; or if
index
is greater than or equal to
srcLen
.
ippStsSrcSizeLessExpected
Indicates a warning if size of the source buffer is insufficient to store all output elements.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804