Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DecodeHuff_BZ2

Performs the bzip2-specific Huffman decoding.

Syntax

IppStatus ippsDecodeHuff_BZ2_8u16u(Ipp32u*
pCode
, int*
pCodeLenBits
, Ipp8u**
ppSrc
, int*
pSrcLen
, Ipp16u*
pDst
, int*
pDstLen
, IppDecodeHuffState_BZ2*
pDecodeHuffState
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pCode
Pointer to the bit buffer.
pCodeLenBits
Number of valid bits in the bit buffer.
ppSrc
Double pointer to the source vector.
pSrcLen
Pointer to the size of source buffer.
pDst
Pointer to the destination vector.
pDstLen
Pointer to the size of destination buffer on input, pointer to the resulting length of the destination vector on output.
pDecodeHuffState
Pointer to internal state structure for bzip2 specific Huffman decoding.
Description
This function performs the bzip2-specific Huffman decoding. The function uses the bzip2-specific Huffman decoding state structure
pDecodeHuffState
. This structure must be initialized by
ippsDecodeHuffInit_BZ2
beforehand.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the pointers is
NULL
.
ippStsSizeErr
Indicates an error if length of the destination buffer is less than or equal to 0.
ippStsSrcSizeLessExpected
Indicates a warning if size of the source buffer is insufficient to store all output elements.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804