Developer Reference

  • 2020
  • 10/21/2020
  • Public Content
Contents

EncodeLZ4HC

Performs LZ4 encoding in HC mode.

Syntax

IppStatus ippsEncodeLZ4HC_8u(const Ipp8u*
pSrc
, int
srcIdx
, int*
pSrcLen
, Ipp8u*
pDst
, int*
pDstLen
, Ipp8u**
ppHashTables
, const Ipp8u*
pDict
, int
dictLen
, int
level
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source data.
srcIdx
Index of the starting byte in the source vector.
pSrcLen
Pointer to the length of the source data for compression.
pDst
Pointer to the compressed data.
pDstLen
Pointer to the length of the compressed data.
ppHashTables
Pointer to an array of pointers to the LZ4 hash tables for HC mode;
ppHashTables[0]
=
pHashTable
,
ppHashTables[1]
=
pPrevTable
.
pDict
Pointer to the dictionary.
dictLen
Length to the dictionary.
level
Compression level.
Description
This function performs encoding of the source data
pSrc
using the LZ4 algorithm. The destination buffer must have sufficient length for the operation. The length of the compressed data is set to
pDstLen
.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if at least one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error if the
srcLen
value is less than, or equal to zero.
ippStsBadArgErr
Indicates an error if the index of the starting byte is less than zero.
ippStsNotSupportedModeErr
Indicates an error if the function does not support the specified combination of parameters' values.

Example



    
/******************************************************************************* * Copyright 2017-2020 Intel Corporation. * * This software and the related documents are Intel copyrighted materials, and * your use of them is governed by the express license under which they were * provided to you (License). Unless the License provides otherwise, you may not * use, modify, copy, publish, distribute, disclose or transmit this software or * the related documents without Intel's prior written permission. * * This software and the related documents are provided as is, with no express * or implied warranties, other than those that are expressly stated in the * License. *******************************************************************************/ /* The example below shows how to use the functions: ippsEncodeLZ4HCHashTableGetSize_8u ippsEncodeLZ4HCHashTableInit_8u ippsEncodeLZ4HC_8u ippsDecodeLZ4_8u */ #include <stdio.h> #include <string.h> #include <ippdc.h> #include <ipps.h> /* Next two defines are created to simplify code reading and understanding */ #define EXIT_MAIN exitLine: /* Label for Exit */ #define check_sts(st) if((st) != ippStsNoErr) goto exitLine; /* Go to Exit if Intel(R) Integrated Primitives (Intel(R) IPP) function returned status different from ippStsNoErr */ #define TEST_SIZE (1024) static int checkDecompr(Ipp8u* decomprAddr, int decomprLen, Ipp8u* srcAddr, int srcLen); int main(void) { Ipp8u *srcBuf = NULL, *comprBuf = NULL, *decomprBuf = NULL, *hashTable = NULL, *prevTable = NULL; Ipp8u *tables[2]; IppStatus st = ippStsNoErr; int hashSize = 0, prevSize = 0, srcLen = TEST_SIZE, comprLen = TEST_SIZE + TEST_SIZE / 255 + 16, /* Extra bytes for uncompressible data */ decomprLen = TEST_SIZE + 33; /* Spare bytes for "wild" (non-safe) decompression */ int i; srcBuf = ippsMalloc_8u(TEST_SIZE); decomprBuf = ippsMalloc_8u(decomprLen); comprBuf = ippsMalloc_8u(comprLen); /* Initialize source buffer */ check_sts( st = ippsVectorJaehne_8u(srcBuf, TEST_SIZE, IPP_MAX_8U) ) for(i = 0; i < TEST_SIZE; i++) srcBuf[i] >>= 6; /* Decrease source data entropy */ /* Init and allocate hash table */ check_sts( st = ippsEncodeLZ4HCHashTableGetSize_8u(&hashSize, &prevSize) ) hashTable = ippsMalloc_8u(hashSize); prevTable = ippsMalloc_8u(prevSize); tables[0] = hashTable; tables[1] = prevTable; check_sts( st = ippsEncodeLZ4HCHashTableInit_8u(tables) ) /* Compress source data at level 1*/ check_sts( st = ippsEncodeLZ4HC_8u((const Ipp8u*)srcBuf, 0, &srcLen, comprBuf, &comprLen, tables, NULL, 0, 1) ) /* Print compression result */ printf("Compression lev 1: %d bytes compressed into %d bytes\n", TEST_SIZE, comprLen); /* Decompression */ decomprLen = TEST_SIZE + 33; check_sts( st = ippsDecodeLZ4_8u((const Ipp8u*)comprBuf, comprLen, decomprBuf, &decomprLen) ) check_sts( st = checkDecompr(decomprBuf, decomprLen, srcBuf, srcLen) ) /* Compress source data at level 6*/ comprLen = TEST_SIZE + TEST_SIZE / 255 + 16; check_sts( st = ippsEncodeLZ4HC_8u((const Ipp8u*)srcBuf, 0, &srcLen, comprBuf, &comprLen, tables, NULL, 0, 6) ) /* Print compression result */ printf("Compression lev 6: %d bytes compressed into %d bytes\n", TEST_SIZE, comprLen); /* Decompression */ decomprLen = TEST_SIZE + 33; check_sts( st = ippsDecodeLZ4_8u((const Ipp8u*)comprBuf, comprLen, decomprBuf, &decomprLen) ) check_sts( st = checkDecompr(decomprBuf, decomprLen, srcBuf, srcLen) ) /* Compress source data at level 9*/ comprLen = TEST_SIZE + TEST_SIZE / 255 + 16; check_sts( st = ippsEncodeLZ4HC_8u((const Ipp8u*)srcBuf, 0, &srcLen, comprBuf, &comprLen, tables, NULL, 0, 9) ) /* Print compression result */ printf("Compression lev 9: %d bytes compressed into %d bytes\n", TEST_SIZE, comprLen); /* Decompression */ decomprLen = TEST_SIZE + 33; check_sts( st = ippsDecodeLZ4_8u((const Ipp8u*)comprBuf, comprLen, decomprBuf, &decomprLen) ) st = checkDecompr(decomprBuf, decomprLen, srcBuf, srcLen); EXIT_MAIN ippsFree(srcBuf); ippsFree(comprBuf); ippsFree(decomprBuf); ippsFree(hashTable); ippsFree(prevTable); return (int)st; } static IppStatus checkDecompr(Ipp8u* decomprAddr, int decomprLen, Ipp8u* srcAddr, int srcLen) { /* Check */ if(decomprLen != srcLen || memcmp(decomprAddr, srcAddr, srcLen) != 0) { printf("Wrong decompression!\n"); return ippStsErr; } printf("Decompressed OK into %d bytes\n", decomprLen); return ippStsNoErr; }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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