Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

EncodeLZ4HashTableInit
,
EncodeLZ4DictHashTableInit

Initializes the LZ4 hash table.

Syntax

IppStatus ippsEncodeLZ4HashTableInit_8u(Ipp8u*
pHashTable
, int
srcLen
);
IppStatus ippsEncodeLZ4DictHashTableInit_8u(Ipp8u*
pHashTable
, int
srcLen
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pHashTable
Pointer to the LZ4 hash table.
srcLen
Length of the source data for compression.
Description
This function initializes the LZ4 hash table. Before using this function, compute the size of the LZ4 hash table using the
EncodeLZ4HashTableGetSize
function.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if the
pHashTable
pointer is
NULL
.
ippStsSizeErr
Indicates an error if the
srcLen
value is less than, or equal to zero.

Example

/******************************************************************************* * Copyright 2015-2020 Intel Corporation. * * This software and the related documents are Intel copyrighted materials, and * your use of them is governed by the express license under which they were * provided to you (License). Unless the License provides otherwise, you may not * use, modify, copy, publish, distribute, disclose or transmit this software or * the related documents without Intel's prior written permission. * * This software and the related documents are provided as is, with no express * or implied warranties, other than those that are expressly stated in the * License. *******************************************************************************/ /* The example below shows how to use the functions: ippsEncodeLZ4HashTableGetSize_8u ippsEncodeLZ4HashTableInit_8u ippsEncodeLZ4_8u ippsDecodeLZ4_8u */ #include <stdio.h> #include <string.h> #include <ippdc.h> #include <ipps.h> /* Next two defines are created to simplify code reading and understanding */ #define EXIT_MAIN exitLine: /* Label for Exit */ #define check_sts(st) if((st) != ippStsNoErr) goto exitLine; /* Go to Exit if Intel(R) Integrated Primitives (Intel(R) IPP) function returned status different from ippStsNoErr */ #define TEST_SIZE (1024) int main(void) { Ipp8u *srcBuf = NULL, *comprBuf = NULL, *decomprBuf = NULL, *hashTable = NULL; IppStatus st = ippStsNoErr; int hashSize = 0, comprLen = TEST_SIZE + TEST_SIZE / 255 + 16, /* Extra bytes for uncompressible data */ decomprLen = TEST_SIZE + 33; int i; srcBuf = ippsMalloc_8u(TEST_SIZE); decomprBuf = ippsMalloc_8u(decomprLen); /* Spare bytes for "wild" (non-safe) decompression */ comprBuf = ippsMalloc_8u(comprLen); /* Initialize source buffer */ check_sts( st = ippsVectorJaehne_8u(srcBuf, TEST_SIZE, IPP_MAX_8U) ) for(i = 0; i < TEST_SIZE; i++) srcBuf[i] >>= 6; /* Decrease source data entropy */ /* Init and allocate hash table */ check_sts( st = ippsEncodeLZ4HashTableGetSize_8u(&hashSize) ) hashTable = ippsMalloc_8u(hashSize); check_sts( st = ippsEncodeLZ4HashTableInit_8u(hashTable, TEST_SIZE) ) /* Compress source data */ check_sts( st = ippsEncodeLZ4_8u((const Ipp8u*)srcBuf, TEST_SIZE, comprBuf, &comprLen, hashTable) ) /* Print compression result */ printf("Compression: %d bytes compressed into %d bytes\n", TEST_SIZE, comprLen); /* Decompression */ decomprLen = TEST_SIZE + 33; check_sts( st = ippsDecodeLZ4_8u((const Ipp8u*)comprBuf, comprLen, decomprBuf, &decomprLen) ) /* Check */ if(decomprLen == TEST_SIZE)/* Decompressed size must be equal to source data size */ { if(memcmp(srcBuf, decomprBuf, TEST_SIZE) != 0) { printf("Wrong decompression!\n"); st = ippStsErr; } else printf("Decompressed by ippsDecodeLZ4_8u OK\n"); } else printf("Invalid decompressed length %d\n", decomprLen); EXIT_MAIN ippsFree(srcBuf); ippsFree(comprBuf); ippsFree(decomprBuf); ippsFree(hashTable); return (int)st; }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804