Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DecodeLZSS

Performs LZSS decoding.

Syntax

IppStatus ippsDecodeLZSS_8u (Ipp8u**
ppSrc
, int*
pSrcLen
, Ipp8u**
ppDst
, int*
pDstLen
, IppLZSSState_8u*
pLZSSState
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
ppSrc
Double pointer to the source buffer.
pSrcLen
Pointer to the length of the source buffer.
ppDst
Double pointer to the destination buffer.
pDstLen
Pointer to the length of the destination buffer.
pLZSSState
Pointer to the LZSS decoding state structure.
Description
This function performs LZSS decoding of the
pSrcLen
elements of the
ppSrc
source buffer and stores the result in the
pDst
destination vector. The length of the destination vector is stored in
pDstLen
. The LZSS decoder state structure
pLZSSState
must be initialized by
ippsDecodeLZSSInit
beforehand.
After decoding the function returns the pointers to source and destination buffers shifted by the number of successfully read and decoded bytes respectively. The function updates
pSrcLen
so it is equal to the actual number of elements in the source buffer.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error if
pSrcLen
or
pDstLen
is negative.
ippStsDstSizeLessExpected
Indicates a warning that the size of the destination buffer is insufficient for completing the operation.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804