Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DeflateUpdate Hash

Performs LZ77 encoding according to the specified compression level.

Syntax

IppStatus ippsDeflateUpdateHash_8u(const Ipp8u*
pSrc
, Ipp32u
srcIdx
, Ipp32u
srcLen
, Ipp32s*
pHashHeadDst
, Ipp32u
hashSize
, Ipp32s*
pHashPrevDst
, Ipp32u
winSize
, int
comprLevel
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source vector.
srcIdx
Index of the current position in the source vector.
srcLen
Length of the source vector.
pHashHeadDst
Pointer to the table containing heads of the hash chains.
hashSize
Size of the
pHashHeadDst
table.
pHashPrevDst
Pointer to the table contating indexes to the previous strings with the same hash key.
winSize
Size of the sliding window and the
pHashPrevDst
table.
comprLevel
Compression level in range [0..9] in accordance with ZLIB.
Description
This function updates hash tables according to the source context.
The function parameter
srcIdx
- index of the current position in the source vector - is used to correlate the current position in the source vector and indexes in the hash tables. After processing each 2GB of source data, this index and hash tables must be normalized (instead of 64K of source data in ZLIB).
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error if
winSize
is less than or equal to 256, or greater than 32768; or if
hashSize
is less than or equal to 256, or greater than 65536.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804