Developer Reference

  • 2020
  • 10/21/2020
  • Public Content
Contents

InflateBuildHuffTable

Builds the Huffman code table for compressed block in the “deflate” format.

Syntax

IppStatus ippsInflateBuildHuffTable(const Ipp16u*
pCodeLens
, unsigned int
nLitCodeLens
, unsigned int
nDistCodeLens
, IppInflateState*
pIppInflateState
);
Include Files
ippdc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pCodeLens
Pointer to the common array with lengths of the Huffman codes for literals/lengths and distances.
nLitCodeLens
Number of lengths of the Huffman codes for literals/lengths.
nDistCodeLens
Number of lengths of the Huffman codes for distances.
pIppInflateState
Pointer to the structure with the parameters of decoding.
Description
This function builds tables of Hufman codes for literals/lengths and distances to decode a block compressed with use of the dynamic Huffman codes in accordance with the “deflate” format [RFC1951].
The structure
IppInflateState
contains the following fields:
pWindow
Pointer to the sliding window (the dictionary for the LZ77 algorithm).
winSize
Size of the sliding window in the range [256, 32768].
tableType
Type of the Huffman code tables. For dynamic Huffman code it is greater than 0, for fixed Huffman codes is equal to 0.
tableBufferSize
Size of the buffer containing the tables. Its value is
8192 - sizeof(IppInflateState)
. (
8192 =
ENOUGH*sizeof(code); ENOUGH
is defined in ZLIB and is equal to
2048
,
sizeof(code)=4.)
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the pointers is
NULL
.
ippStsSizeErr
Indicates an error if
nLitCodeLens
is greater than 286 or
nDistCodeLens
is greater than 30.
ippStsSrcDataErr
Indicates an error if a not valid literal/length and distance set occurs in the common lengths array.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804