Intel® Integrated Performance Primitives Developer Reference

Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

SortIndexAscend
 ,
SortIndexDescend

Rearranges elements of the vector and their indexes.

Syntax

IppStatus ippsSortIndexAscend_8u_I(Ipp8u*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexAscend_16u_I(Ipp16u*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexAscend_16s_I(Ipp16s*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexAscend_32s_I(Ipp32s*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexAscend_32f_I(Ipp32f*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexAscend_64f_I(Ipp64f*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_8u_I(Ipp8u*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_16u_I(Ipp16u*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_16s_I(Ipp16s*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_32s_I(Ipp32s*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_32f_I(Ipp32f*
pSrcDst
, int*
pDstIdx
, int
len
);
IppStatus ippsSortIndexDescend_64f_I(Ipp64f*
pSrcDst
, int*
pDstIdx
, int
len
);
Include Files
ipps.h
Domain Dependencies
Headers:
ippcore.h
 ,
ippvm.h
Libraries:
ippcore.lib
 ,
ippvm.lib
Parameters
pSrcDst
 Pointer to the source and destination vector.
pDstIdx
 Pointer to the destination vector containing indexes.
len
 Number of elements in the vector
Description
These functions rearrange all elements of the source vector
pSrcDst
 in the ascending or descending order, respectively, and store the elements in the destination vector
pSrcDst
 , and their indexes in the desalination vector
pDstIdx
 . If some elements are identical, their indexes are not ordered.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
 .
ippStsSizeErr
Indicates an error when
len
 is less than or equal to 0.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804