Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

Not

Computes the bitwise NOT of the vector elements.

Syntax

IppStatus ippsNot_8u(const Ipp8u*
pSrc
, Ipp8u*
pDst
, int
len
);
IppStatus ippsNot_16u(const Ipp16u*
pSrc
, Ipp16u*
pDst
, int
len
);
IppStatus ippsNot_32u(const Ipp32u*
pSrc
, Ipp32u*
pDst
, int
len
);
IppStatus ippsNot_8u_I(Ipp8u*
pSrcDst
, int
len
);
IppStatus ippsNot_16u_I(Ipp16u*
pSrcDst
, int
len
);
IppStatus ippsNot_32u_I(Ipp32u*
pSrcDst
, int
len
);
Include Files
ipps.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
Libraries:
ippcore.lib
,
ippvm.lib
Parameters
pSrc
Pointer to the source vector.
pDst
Pointer to the destination vector.
pSrcDst
Pointer to the source and destination vector for the in-place operation.
len
Number of elements in the vector.
Description
This function computes the bitwise NOT of the corresponding elements of the vectors
pSrc
, and stores the result in the vector
pDst
.
The in-place flavors of
ippsNot
compute the bitwise NOT of the corresponding elements of the vector
pSrcDst
and store the result in the vector
pSrcDst
.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when the
pSrc
,
pDst
, or
pSrcDst
pointer is
NULL
.
ippStsSizeErr
Indicates an error when
len
is less than or equal to 0.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804