Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

FIRMRGetSize

Computes the size of the context structure and work buffer for multi-rate FIR filtering.

Syntax

Case 1: Operation on a signal that has the same data type as the coefficients
IppStatus ippsFIRMRGetSize(int
tapsLen
, int
upFactor
, int
downFactor
, IppDataType
tapsType
, int*
pSpecSize
, int*
pBufSize
);
Case 2: Operation on a signal that has a data type different from the data type of the coefficients
IppStatus ippsFIRMRGetSize32f_32fc(int
tapsLen
, int
upFactor
, int
downFactor
, int*
pSpecSize
, int*
pBufSize
);
Include Files
ipps.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
Libraries:
ippcore.lib
,
ippvm.lib
Parameters
tapsLen
Length of the FIR filter.
upFactor
Multi-rate up factor.
downFactor
Multi-rate down factor.
tapsType
Data type of the coefficients. Supported values are
Ipp32f
,
Ipp32fc
,
Ipp64f
, and
Ipp64fc
.
pSpecSize
Pointer to the size of the FIR specification structure.
pBufSize
Pointer to the size of the work buffer required for FIR filtering.
Description
This function computes the following:
  • Size of the internal specification structure for multi-rate FIR filtering. The structure can be shared between all threads of the application.
  • Size of the work buffer for each thread.
For an example on how to use this function, refer to the example provided with the
FIRMR
function description.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error when the
tapsLen
value is less than or equal to zero.
ippStsDataTypeErr
Indicates an error when the specified taps type is not supported.
ippStsFIRMRFactorErr
Indicates an error when the
upFactor
value or the
downFactor
value is less than zero.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804