Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

IIRGetStateSize_BiQuad

Computes the length of the external buffer for the biquad IIR filter state structure.

Syntax

IppStatus ippsIIRGetStateSize32f_BiQuad_16s(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64f_BiQuad_16s(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64f_BiQuad_32s(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize32fc_BiQuad_16sc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64fc_BiQuad_16sc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64fc_BiQuad_32sc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize_BiQuad_32f(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64f_BiQuad_32f(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize_BiQuad_64f(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize_BiQuad_32fc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64fc_BiQuad_32fc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize_BiQuad_64fc(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize64f_BiQuad_DF1_32s(int
numBq
, int*
pBufferSize
);
IppStatus ippsIIRGetStateSize_BiQuad_DF1_32f(int
numBq
, int*
pBufferSize
);
Include Files
ipps.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
Libraries:
ippcore.lib
,
ippvm.lib
Parameters
numBq
Number of cascades of biquads.
pBufferSize
Pointer to the computed buffer size value.
Description
This function computes the size of the external buffer for a corresponding biquad IIR filter state, and stores the result in
pBufferSize
.
To compute a size of the buffer, the number of cascades of biquads
numBq
must be specified.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when
pBufferSize
pointer is
NULL
.
ippStsIIROrderErr
Indicates an error when
numBq
is less than or equal to 0.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804