Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

FIRLMSInit

Initializes the adaptive FIR least mean squares (LMS) filter state structure.

Syntax

IppStatus ippsFIRLMSInit32f_16s(IppsFIRLMSState32f_16s**
ppState
, const Ipp32f*
pTaps
, int
tapsLen
, const Ipp16s*
pDlyLine
, int
dlyIndex
, Ipp8u*
pBuffer
);
IppStatus ippsFIRLMSInit_32f(IppsFIRLMSState_32f**
ppState
, const Ipp32f*
pTaps
, int
tapsLen
, const Ipp32f*
pDlyLine
, int
dlyIndex
, Ipp8u*
pBuffer
);
Include Files
ipps.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
Libraries:
ippcore.lib
,
ippvm.lib
Parameters
ppState
Double pointer to the state structure.
pTaps
Pointer to the array of tap values.
tapsLen
Number of elements in the array containing tap values.
pDlyLine
Pointer to the array containing delay line values. The number of elements in the array is 2*
tapsLen
.
dlyIndex
Current index of the delay line.
pBuffer
Pointer to the external buffer for the FIR LMS state structure.
Description
This function initializes the single-rate FIR LMS filter state structure. The
ippsFIRLMSInit
function copies the taps from the
pTaps
array of
tapsLen
length into the state structure
ppTaps
. The
pDlyLine
array of size 2*
tapsLen
specifies the delay line values. The current index of the delay line is defined by
dlyIndex
. If the pointer to
pDlyLine
or
pTaps
is
NULL
, the corresponding value of the state structure is initialized to zero.
To compute the size of the buffer required for the FIR LMS state structure, use the
ippsFIRLMSGetStateSize
function.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when either
ppState
or
pBuffer
is
NULL
.
ippStsFIRLenErr
Indicates an error when
tapsLen
is less than, or equal to zero.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804